The present disclosure provides a memory device test method, apparatus, and system, a medium, and an electronic device. The memory device test method includes: determining an operation path according to position coordinates of a target test platform and current position coordinates of a memory device; setting a movable apparatus according to the operation path, such that the movable apparatus moves the memory device into the target test platform according to the operation path; controlling the target test platform to test the memory device according to a target test program; and monitoring a test result of the memory device in real time, and storing the test result of the memory device into a database.

A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack; and (c) an array of POP memory devices, wherein each POP memory device is disposed adjacent to a respective DUT in the array of DUTs. Further, the testing apparatus comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.

According to one embodiment, a storage device includes a stage on which a semiconductor wafer can be mounted, wherein data is capable of being read from the semiconductor wafer or data is capable of being written to the semiconductor wafer. The storage device further includes a plurality of probe pins for reading or writing data, and a controller connected the probe pins. The semiconductor wafer includes electrodes connectable to the probe pins, a first memory area that can store user data, and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information. The controller is capable of reading the identification information and the check code from the second memory area.

A clamping module is adapted to clamp a memory module and insert or remove the memory module into/from a slot. The clamping module includes a main body, two jaw clamps and a blocking pressing plate. The two jaw clamps are movably disposed on the main body and adapted to move in relative to each other to clamp or release the memory module. The blocking pressing plate is movably disposed on the main body, wherein after the two jaw clamps clamp the memory module to a position in contact with the slot, the two jaw clamps moves away from each other so that the memory module is released and the blocking pressing plate moves from a first position to a second position in order to press the memory module so that the memory module is inserted into the slot.

A technique relates probing a pass gate transistor in a static random access memory (SRAM) circuit. A gate probe is connected to a gate metal layer of the SRAM circuit, the gate metal layer being coupled to a gate of the pass gate transistor. A source probe is connected to a source metal layer of the SRAM circuit, the source metal layer being coupled to a source of the pass gate transistor. A drain probe is connected to a drain metal layer of the SRAM circuit, the drain metal layer being coupled to a drain of the pass gate transistor, the SRAM circuit comprising other transistors along with the pass gate transistor. The other transistors are free from connections for the probing so as not to cause the other transistors to have an unwanted effect on the pass gate transistor being probed.

The present disclosure provides a method of testing a testing device with a ground noise. The method includes coupling a device under test in series between a source and a ground in an automatic test equipment, coupling a ground bounce generator in series between the device under test and the ground, coupling the testing device to the device under test, providing a current by the source through the device under test and the ground bounce generator, controlling the ground bounce generator to generate the ground noise, and collecting a performance result of the testing device in the automatic test equipment.

A Magnetoresistive Random Access Memory (MRAM) device is tested using a high repetition test that detects one or more low-likelihood failures, such as a failure to properly switch between a high or low resistive state. A series of write and read operations are performed for a large number of test cycles at high frequency. A first tier measurement is used to determine if a switching failure occurred, e.g. by comparing the read signal to target level(s) after each operation. When a switching failure event is detected, a second tier measurement is used to measure and store switching performance parameters, for example, the value of the read signal, while the MRAM device is in a failure state. The high frequency testing may be paused during the second tier measurements. Additional performance parameters may be measured during the second tier measurements.

A probe device includes a first receiving terminal configured to receive a multi-level signal having M levels, where M is a natural number greater than 2; a second receiving terminal configured to receive a reference signal; a receiving buffer including a first input terminal connected to the first receiving terminal, a second input terminal connected to the second receiving terminal, and an output terminal configured to output the multi-level signal based on signals received from the first and second input terminals; and a resistor circuit comprising a plurality of resistors connected to the first and second receiving terminals and determining a magnitude of a termination resistance of the first and second receiving terminals.

A test system for a memory card includes a first circuit board. One side of the first circuit board is provided with a plurality of contact groups spaced apart from each other along a row direction. Another side of the first circuit board is provided with slots disposed along the row direction. The test system further includes a second circuit board. The second circuit board is provided with a test circuit, and is inserted into the slot along a direction perpendicular to the first circuit board. The second circuit board provides a test signal to the contact groups.

According to one embodiment, in a memory system, a printed circuit board a first end portion and a second end portion. The second end portion is a portion arranged in an opposite side of the first end portion. Both of a semiconductor memory and a controller are disposed on the first surface. A edge connector is connectable to a host device and is disposed in the first end portion. Plural through-hole portions are disposed in the second end portion. Each of the plural through-hole portions penetrates from the first surface to the second surface. Each of the plural through-hole portions has an inner surface covered with an electrically-conductive film. Plural pad electrodes are disposed on the second surface in the second end portion. At least some of the plural through-hole portions are electrically connected to the controller. At least some of the plural pad electrodes are electrically connected to the controller.