A memory test system may include a tester and N memory devices, where N is a positive integer greater than 1. The tester may generate test signals. A K-th memory device of the N memory devices includes a plurality of K-th memory banks and a K-th decoder, where K is each positive integer equal to or smaller than N. The K-th memory banks may be configured to operate based on first internal signals and each of the K-th memory banks includes a plurality of unit blocks. The K-th decoder may be configured to convert the test signals corresponding to the first test to the first internal signals based on a K-th conversion relation and update the K-th conversion relation based on a result of the first test with respect to the K-th memory device.

A marker pattern for enhancing resolution of a defect location along an axis in semiconductor defect analysis, and in particular, a marker pattern providing greater resolution in locating bit line defects using thermal laser stimulation methods such as OBIRCH. In an example, the marker pattern may consist of large markers, each having a set of associated small markers. Each of the small markers may be offset along an axis from each other. By identifying the small marker and its associated large marker which align with the defect, the bit line containing the defect may be more easily identified.

A system is provided. The system comprises test devices, a transport device and a data processing device. The test devices perform tests different from each other to a memory device and output test results of the tests. The transport device transports the memory device to the test devices and comprises a first storage device. The first storage device stores the test results and a list of a part of test devices that have tested the memory device. The data processing device stores fabrication data of the memory device. When the transport device determines that the memory device is defective according to at least one of the test results, the data processing device generates a report according the at least one of the test results and the fabrication data.

A failure analysis and detection method for a memory is configured to perform abnormal bit detection on a memory. The failure analysis and detection method includes: coordinates are marked on a detection area of the memory, and the coordinates are associated with layout design or a process of the detection area; a MOD function is used to perform classification according to regularity of the coordinates, and the MOD function is a function for getting remainder; and failure information corresponding to the classification is obtained from a failure bitmap (FBM) of the detection area, and the failure information includes a failure cause corresponding to the layout design or the process.

Disclosed are a method and system for detecting a memory error, and a device. The method includes: taking an application platform as a test engine of a memory test device, the application platform being provided with a system memory; capturing, by the memory test device, a data flow of an actual application program of the application platform on a memory transmission line in a manner including a logic analyzer; and taking, by the memory test device, a processed data flow as a memory test vector to test a tested memory device, thereby reproducing a memory error of the application platform or the application program on the memory test device. The present disclosure can reproduce all tested memory devices with an error in the application platform, and improves a reproduction rate for the memory error.

A computer-implemented method, according to one approach, includes: in response to a system detecting an initial microcode load, determining whether memory in the system was disarmed during manufacture. The memory in the system is connected to backup power modules. The computer-implemented method also includes monitoring for concurrent code loads in response to determining that the memory was disarmed during manufacture. Moreover, in response to detecting a concurrent code load, the energy levels of the backup power modules are tested. A warning is further issued in response to determining the energy levels of one or more of the backup power modules are outside a predetermined range. Other systems, computer-implemented methods, and computer program products are described in additional approaches.

A method can include performing at least one glitch resistance operation and detecting, by a circuit included in a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.

A method can include performing at least one glitch resistance operation and detecting, by a circuit included in a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.

An electronic device is provided. The electronic device includes dynamic random access memory (DRAM), memory, and one or more processors communicatively coupled to the DRAM and the memory, wherein the memory store one or more computer programs including computer-executable instructions that, when executed by the one or more processors, cause the electronic device to generate a first eye diagram based on training the DRAM with a driving voltage, identify a first parameter in a designated format corresponding to the generated first eye diagram, generate a second eye diagram based on training the DRAM with the driving voltage, compare the identified first parameter with a second parameter in the designated format corresponding to the generated second eye diagram, and adjust the driving voltage based on a result of the comparison between the first parameter and the second parameter.