Disclosed in some examples are methods, systems, memory devices, machine readable mediums configured to intentionally degrade NAND performance when a value of a NAND health metric indicates a potential for failure to encourage users to replace or backup their devices before data loss occurs. For example, the system may track a NAND health metric and when that metric reaches a predetermined threshold or state, the system may intentionally degrade performance. This performance degradation may be more effective than a warning to effect device backup or replacement.

A transconductance test method implemented in a flash memory device detects memory cells with low transconductance and provides an output identifying memory cells, if any, having been classified as having a low transconductance (low g.sub.m). In some embodiments, the transconductance test method implements multi-step testing using a pair of gate bias levels for each test step. Accurate detection of memory cells with low transconductance can be realized.

A device has a digital-to-analog converter to convert waveform data into analog waveforms, a waveform memory to store stored waveform data, an external waveform interface to receive real-time waveform data from an external device, a waveform multiplexer connected to the digital-to-analog converter to select between the first memory and the external waveform interface, a sequencer to receive and execute instructions to identify and access waveform data to drive the digital-to-analog converter, a sequencer instruction memory to provide stored instructions to the sequencer, an external instruction interface to receive real-time instructions for the sequencer, and a sequencer multiplexer to select between the sequencer instruction memory and the external instruction interface connected to the sequencer. A method of controlling a waveform generator includes selecting a mode of operation, where the mode of operation is selected from streaming waveform data, real-time waveform memory updates, real-time sequencer instructions, real-time sequencer instruction updates, and real-time sequencer flow control.

An interface of a memory sub-system can receive a write command addressed to a first address and a read command addressed to a second address and can receive data corresponding to the write command. The interface can determine whether the first address matches the second address responsive to determining that the first address matches the second address, can drop the read command and the second address, and can provide the data to a host.

Apparatuses, systems, methods, and computer program products are disclosed for performing read mode tuning. An apparatus includes an error rate storage circuit that determines error rate information. An apparatus includes a mode selection circuit that determines a read mode of a plurality of read modes for reading a set of memory cells based on error rate information. The plurality of read modes may include a fast read mode and a normal read mode. An apparatus includes a read circuit that performs a read on a set of memory cells based on a read mode.

Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Disclosed in some examples are methods, systems, memory devices, machine readable mediums configured to intentionally degrade NAND performance when a value of a NAND health metric indicates a potential for failure to encourage users to replace or backup their devices before data loss occurs. For example, the system may track a NAND health metric and when that metric reaches a predetermined threshold or state, the system may intentionally degrade performance. This performance degradation may be more effective than a warning to effect device backup or replacement.

Apparatuses, systems, methods, and computer program products are disclosed for performing read mode tuning. An apparatus includes an error rate storage circuit that determines error rate information. An apparatus includes a mode selection circuit that determines a read mode of a plurality of read modes for reading a set of memory cells based on error rate information. The plurality of read modes may include a fast read mode and a normal read mode. An apparatus includes a read circuit that performs a read on a set of memory cells based on a read mode.

Embodiments of the present disclosure provide a memory test method and a device thereof, an electronic device, and a computer-readable storage medium, which relate to the field of semiconductor device testing technologies. The method is executed by a built-in self-test circuit and includes: acquiring defect information of a first memory by testing the first memory; acquiring repair information of the first memory based on the defect information of the first memory; and storing the repair information of the first memory in a second memory.

A memory system includes a semiconductor memory device and a test device. The semiconductor memory device includes a memory cell array, an error correction circuit and a test circuit. The test device controls a test of the semiconductor memory device, and the test device includes a first fail address memory and a second fail address memory. The test circuit performs a first test on the memory cell array to selectively record a first test result associated with the first test in the first fail address memory and performs a second test on the memory cell array to record a second test result associated with the second test in the second fail address memory. The test circuit is configured to perform the first test and the second test based on a test pattern data from the test device in a test mode.