Different embodiments of local redundancy decoder circuits that can be used in a memory device are disclosed. The different types of local redundancy decoder circuits are operably connected to the columns of memory cells in a memory array.

Various embodiments of the present disclosure are directed towards a method for memory repair using a lookup table (LUT)-free dynamic memory allocation process. An array of memory cells having a plurality of rows and a plurality of columns is provided. Further, each memory cell of the array has multiple data states and a permanent state. One or more abnormal memory cells is/are identified in a row of the array and, in response to identifying an abnormal memory cell, the abnormal memory cell is set to the permanent state. The abnormal memory cells include failed memory cells and, in some embodiments, tail memory cells having marginal performance. During a read or write operation on the row, the one or more abnormal memory cells is/are identified by the permanent state and data is read from or written to a remainder of the memory cells while excluding the abnormal memory cell(s).

The present technology relates to an electronic device. According to the present technology, a memory device having reduced latency includes a plurality of memory cells, an optimum read voltage information storage configured to store optimum read voltage information determined according to a cell count value, which is the number of memory cells read as a first memory cell based on data read from the plurality of memory cells among the plurality of memory cells, and a read voltage controller configured to calculate a cell count value corresponding to a default read voltage based on the data read from the plurality of memory cells using the default read voltage, in response to an optimum read voltage setting command input from a memory controller, and generate a first optimum read voltage based on the cell count value corresponding to the default read voltage and the optimum read voltage information.

Many error correction schemes fail to correct for double-bit errors and a module must be replaced when these double-bit errors occur repeatedly at the same address. This helps prevent data corruption. In an embodiment, the addresses for one of the memory devices exhibiting a single-bit error (but not the other also exhibiting a single bit error) is transformed before the internal memory arrays are accessed. This has the effect of moving one of the error prone memory cells to a different external (to the module) address such that there is only one error prone bit that is accessed by the previously double-bit error prone address. Thus, a double-bit error at the original address is remapped into two correctable single-bit errors that are at different addresses.

Methods, systems, and devices for completing memory repair operations interrupted by power loss are described. A command to perform a memory repair of a memory device may be received. A memory repair process of the memory device may be initiated, based on the command. The memory repair process may include programming fuse elements of the memory device. Information associated with the initiated memory repair process may be stored in a non-volatile memory. The memory repair process may be interrupted by a power interruption. During powerup of the memory device, it may be determined that the memory repair process was initiated and not completed before the powerup, based on the stored information. The memory repair process of the memory device may be continued, based on the determination. Upon completion of the memory repair process, the stored information may be cleared.

An integrated circuit self-repair method and an integrated circuit thereof are provided. The integrated circuit self-repair method includes: transmitting, by a main register, a predetermined logic state to at least three registers, and setting the at least three registers to the predetermined logic state; outputting, according to the predetermined logic state in the at least three registers, the predetermined logic state to drive a controlled circuit to perform a function; and when a minority of the at least three registers are changed to an opposite logic state due to an emergency occurring at an input power source, outputting the predetermined logic state according to the predetermined logic state of the remaining registers, and transmitting the predetermined logic state back to the register that is in the opposite logic state, to correct the opposite logic state to the predetermined logic state.

An electronic device includes: a detection circuit configured to determine one or more operating data, one or more device sensor data, or a combination thereof associated with operation of the electronic device; a trigger circuit operably coupled to the circuit, the trigger circuit configured to generate a stress input based on detecting one or more target criteria from the one or more operating data, the one or more device sensor data, or a combination thereof; and a degradation sensor operably coupled to the trigger circuit, the degradation sensor having a threshold voltage and being configured to record the target criteria that occurs during operation of the electronic device, wherein the degradation sensor is configured to record the target criteria based on degradation of the threshold voltage according to the stress input.

An example processing device of a memory sub-system is configured to select, from a plurality of voltage bins associated with a memory device, a first set of voltage bins, wherein each voltage bin is associated with a corresponding set of read level offsets; determine, based on a trigger metric associated with the first set of bins, a first score of the first set of bins; replace at least a first voltage bin of the first set with at least a second voltage bin of the plurality of voltage bins to generate a second set of voltage bins; determine a second score of the second set of voltage bins; and responsive to determining that the second score of the second set of bins is greater than the first score of the first set of voltage bins, utilize the second set of voltage bins for performing read operations of the memory device.

A redundancy analysis method of replacing a faulty part of a memory with at least one spare according to the present embodiment includes: acquiring fault information of the memory; and redundancy-allocating the fault with combinations of the spares to correspond to combination codes corresponding to the combinations of the spares, in which, the redundancy-allocating with the combination of the spare areas includes performing parallel processing on each combination of the spares.

A die-to-die voltage sharing process that may be implemented to overcome a charge pump failure on a memory die of a non-volatile storage device. When a charge pump failure is detected, a controller causes another memory die with a functional charge pump to generate and supply a voltage to the memory die with the failed charge pump. When the voltage is received by the memory die with the failed charge pump, the voltage may be used to perform a requested memory operation.