Embodiments of present disclosure relates to method and apparatus for performing redundancy analysis of a semiconductor device. For the redundancy analysis, plurality of banks in the semiconductor device is classified to be associated with a cluster from plurality of clusters. The classification is based on one or more attributes associated with the plurality of banks. Further, at least one cluster parameter for the plurality of clusters and at least one bank parameter for the plurality of banks, is determined. One or more algorithms is mapped with the plurality of clusters, based on the at least one cluster parameter and the at least one bank parameter. The redundancy analysis of at least one bank in the plurality of clusters is performed based on the mapping.

A resistive memory device and a reliability enhancement method thereof are provided. The reliability enhancement method includes the following steps. A forming operation is performed on a plurality of memory cells. The formed memory cells are read to respectively obtain a plurality of formed currents. A reference current is set according to a statistic value of the formed currents. A setting operation is performed on the memory cells. A ratio between a set current of each of the memory cells and the reference current is calculated, and a physical status of each of the memory cells is judged according to the ratio. It is determined whether to perform a fix operation of each of the memory cells or not according to physical status.

A memory system is provided. The memory system includes an error correction code circuit configured to correct a maximum of N error bits in each of multiple read data and a monitor circuit configured to monitor multiple fail word addresses associated with M error bits, and further configured to output a first word address in the fail word addresses to replace first memory locations corresponding to the first word address. Each of the fail word addresses corresponds to one of multiple counter values, and the first word address corresponds to a maximum value of the counter values.

A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.

Methods, systems, and devices for performing an error correction operation using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. The error correction circuit may operate on the redundancy data and transfer the result of the operation to select components in a connected error correction circuit. The components to which the output is transferred may be selected based on data plane replaced by the redundancy data. The device may generate syndrome bits for the read data by performing additional operations on the outputs of the error correction circuit.

An initial level of sensing voltage is set based on one or more characteristics of the segment of the memory device. A count for operational cycles for a segment of a memory device is set. Responsive to determining that a number of operational cycles performed on the segment of the memory device has reached the set count of operational cycles, the sensing voltage is varied with respect to the initial level of sensing voltage. The sensing voltage is adjusted to a new level based on wearing of the segment of the memory device during the number of operational cycles performed on the segment of the memory device.

Techniques for caching data are provided that include receiving, by a caching system, a write memory command for a memory address, the write memory command associated with a first color tag, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing first data associated with the first write memory command in a cache line of the second sub-cache, storing the first color tag in the second sub-cache, receiving a second write memory command for the cache line, the write memory command associated with a second color tag, merging the second color tag with the first color tag, storing the merged color tag, and evicting the cache line based on the merged color tag.

A method of operating a storage device including a non-volatile memory includes storing program and erase counts of the non-volatile memory as metadata in units of super blocks, wherein each of the super blocks includes a pre-defined number of blocks of the non-volatile memory, performing a read operation on a first block included in a first super block based on a first read level, storing the first read level as a history read level of the first super block in a history buffer when the read operation on the first block is successful, receiving a read request for a second block of the first super block and an address of the second block from a host, and performing a read operation on the second block based on the history read level stored in the history buffer. The pre-defined number is at least two.

A memory system is disclosed. The memory system includes a first memory array, an error correction code circuit, and a monitor circuit. The error correction code circuit is configured to receive data from the first memory array to correct, at least one error bit in the received data. The error correction code circuit is further configured to generate an error determination signal. The monitor circuit is coupled to the error correction code circuit. The monitor circuit is configured to receive the error determination signal and record at least one fail word address associated with the at least one error bit and corresponding failure times in an error table.

A data processing circuit and a fault-mitigating method, which are adapted for a memory having a faulty bit, are provided. The memory is configured to store data related to an image, a weight for a multiply-accumulate (MAC) operation of image feature extraction, and/or a value for an activation operation. Sequence data is written into the memory. The bit number of the sequence data equals to the bit number used for storing data in a sequence block of the memory. The sequence data is accessed from the memory, wherein the access of the faulty bit in the memory is ignored. The value of the faulty bit is replaced by the value of a non-faulty bit in the memory to form new sequence data. The new sequence data is used for MAC. Accordingly, the accuracy of image recognition can be improved for the faulty memory.