A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory cells. The control logic circuit generates a first control signal to control the I/O gating circuit and a second control signal to control the ECC engine, in response to an access address and a command. The control logic circuit controls the ECC engine to perform s-bit ECC encoding on a write data to be stored in a first page of at least one bank array, in response to a first command, and controls the ECC engine to perform t-bit ECC decoding on a first codeword read from the first page, in response to a second command.

A non-volatile memory system comprises an integrated memory assembly in communication with a memory controller. The integrated memory assembly comprises a memory die bonded to a control die with bond pads. The control die includes one or more control circuits for controlling the operation of the memory die. The one or more control circuits are configured to receive data to be programmed into the memory die, select a number of parity bits, encode the data to add error correction information and form a codeword that includes the number of parity bits, shape the codeword, and program the shaped codeword into the memory die.

Numerous embodiments are disclosed of improved architectures for storing and retrieving system data in a non-volatile memory system. Using these embodiments, system data is much less likely to become corrupted due to charge loss, charge redistribution, disturb effects, and other phenomena that have caused corruption in prior art non-volatile memory systems.

Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.

A computing system is disclosed. The computing system includes a computation unit, one or more processors, a volatile memory, and a non-volatile memory communicatively coupled to the one or more processors and having instructions stored thereon, which when executed by the one or more processors, causing the one or more processor to instantiate a container and perform at least one of a volatile memory checking procedure or a non-volatile memory checking procedure. The volatile memory checking procedure includes checking the first physical address space for errors, loading a container into volatile memory containing the first physical address space if an error is determined, rechecking the first physical address space for error, loading the container to a second physical address space and updating a memory management unit if an error in the first physical address space is determined.

A controller includes an interface and storage circuitry. The interface is configured to communicate with a memory device that includes multiple memory cells organized in memory blocks. The memory device supporting programming of the memory cells with enabled or disabled program-verification. The storage circuitry is configured to disable the program-verification, and program data to a group of the memory cells in a Single Level Cell (SLC) mode using a single programming pulse, to read the data from the group of the memory cells. In response to detecting a failure in reading the data, the storage circuitry is configured to distinguish between whether the memory cells in the group belong to a defective memory block or were under-programmed, and when identifying that the memory cells in the group were under-programmed, to perform a corrective action to prevent under-programming in subsequent program operations to the memory cells in the group.

Methods, systems, and devices for performing an error correction operation using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. The error correction circuit may operate on the redundancy data and transfer the result of the operation to select components in a connected error correction circuit. The components to which the output is transferred may be selected based on data plane replaced by the redundancy data. The device may generate syndrome bits for the read data by performing additional operations on the outputs of the error correction circuit.

A storage system has a memory with primary and secondary blocks. Data is stored redundantly in the primary and secondary memory blocks but in a different programming order. For example, data is programmed in the first memory block starting at a first wordline and ending at a last wordline, while data is programmed in the second memory block starting at the last wordline and ending at the first wordline.

A data processing circuit and a fault-mitigating method, which are adapted for a memory having a faulty bit, are provided. The memory is configured to store data related to an image, a weight for a multiply-accumulate (MAC) operation of image feature extraction, and/or a value for an activation operation. Sequence data is written into the memory. The bit number of the sequence data equals to the bit number used for storing data in a sequence block of the memory. The sequence data is accessed from the memory, wherein the access of the faulty bit in the memory is ignored. The value of the faulty bit is replaced by the value of a non-faulty bit in the memory to form new sequence data. The new sequence data is used for MAC. Accordingly, the accuracy of image recognition can be improved for the faulty memory.

The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.