Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed (and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.

According to certain embodiments, a memory module is operable with a memory controller of a host system. The memory module includes a module controller configurable to receive address and control signals from the memory controller, and dynamic random access memory elements configurable to communicate data signals with the memory controller in accordance with the address and control signals. The module controller has an open-drain output and is configurable to drive the open-drain output with a first signal to indicate a parity error having occurred when the memory module is being accessed for a normal memory read or write operation. The module controller is further configurable to drive the open drain output with a second signal related to one or more training sequences when the memory module performs operations associated with the one or more training sequences and not associated with any normal memory read or write operations.

Various embodiments described herein provide for a page program sequence for a block of a memory device, such as a negative-and (NAND)-type memory device, where all the wordlines are programmed with respect to a given set of page types (e.g., LP pages) prior to wordlines are programmed with respect to a next set of page types (e.g., UP and XP pages).

Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed (and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.

A memory may include a first repair analysis circuit suitable for storing an input fail address when the input fail address is different from a fail address which is already stored in the first repair analysis circuit, and outputting the input fail address as a first transfer fail address when a storage capacity of the first repair analysis circuit is full; and a second repair analysis circuit suitable for storing the first transfer fail address when the first transfer fail address is different from a fail address which is already stored in the second repair analysis circuit.

A memory device that includes a memory array, a program circuit, a verify circuit and a controller is introduced. The program circuit is configured to apply a program pulse to at least one memory cell to set the at least one memory cell to a target state. The verify circuit is configured to perform a verify operation to determine whether the at least one memory cell reaches the predetermine threshold and to determine a number of failed memory cells among the at least one memory cell in response to determining that at least one of the at least one memory cell does not reach the target state. The controller is configured to adjust the program pulse according to the number of the failed memory cells to generate an adjusted program pulse that is applied to the failed memory cells to set the failed memory cells to the target state.

Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.

Various embodiments described herein provide for a page program sequence for a block of a memory device, such as a negative-and (NAND)-type memory device, where all the wordlines are programmed with respect to a given set of page types (e.g., LP pages) prior to wordlines are programmed with respect to a next set of page types (e.g., UP and XP pages).

A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.