A method of failure mapping is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes as a storage cluster. Each of the plurality of storage nodes has a non-volatile solid-state storage with flash memory or other types of non-volatile memory and the user data is accessible via the erasure coding from a remainder of the plurality of storage nodes in event of two of the plurality of storage nodes being unreachable. The method includes determining that a non-volatile memory block in the memory has a defect and generating a mask that indicates the non-volatile memory block and the defect. The method includes reading from the non-volatile memory block with application of the mask, wherein the reading and the application of the mask are performed by the non-volatile solid-state storage.

A method for testing a memory chip including: performing an electrical die sorting (EDS) test on the memory chip; performing a package test when the EDS test is passed; performing a module test when the package test is passed; performing a mounting test when the module test is passed; and setting the memory chip to a mirroring mode through a fusing operation when the EDS test, tire package test, tire module test or the mounting test is failed.

A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

Methods, systems, and devices for completing memory repair operations interrupted by power loss are described. A command to perform a memory repair of a memory device may be received. A memory repair process of the memory device may be initiated, based on the command. The memory repair process may include programming fuse elements of the memory device. Information associated with the initiated memory repair process may be stored in a non-volatile memory. The memory repair process may be interrupted by a power interruption. During powerup of the memory device, it may be determined that the memory repair process was initiated and not completed before the powerup, based on the stored information. The memory repair process of the memory device may be continued, based on the determination. Upon completion of the memory repair process, the stored information may be cleared.

A data processing circuit and a fault-mitigating method, which are adapted for a memory having a faulty bit, are provided. The memory is configured to store data related to an image, a weight for a multiply-accumulate (MAC) operation of image feature extraction, and/or a value for an activation operation. Sequence data is written into the memory. The bit number of the sequence data equals to the bit number used for storing data in a sequence block of the memory. The sequence data is accessed from the memory, wherein the access of the faulty bit in the memory is ignored. The value of the faulty bit is replaced by the value of a non-faulty bit in the memory to form new sequence data. The new sequence data is used for MAC. Accordingly, the accuracy of image recognition can be improved for the faulty memory.

The present disclosure provides an operation method related to a post package repair (PPR) function in a dynamic random access memory (DRAM) device. The method for operating a post package repair (PPR) function of a memory device is disclosed. The method includes providing a memory bank, which includes a memory array and a sense amplifier adjacent to the memory array, wherein the memory array comprises at least one defective row and at least one associated row, and the at least one associated row is electrically connected to the sense amplifier by a plurality of bit lines. The method also includes arranging a redundant row adjacent to the memory array, wherein the redundant row is electrically connected to the sense amplifier by the plurality of bit lines. The method also includes activating the at least one associated row to transmit data in the at least one associated row to the sense amplifier, latching the data in the sense amplifier; activating the redundant row, and transmitting the data from the sense amplifier to the redundant row.

A system includes a memory component, and a processing device coupled with the memory component. The processing device to identify a group of management units of the memory component, wherein the group of management units is included in a set of retired groups of management units, select a management unit from the group of management units, perform a media integrity check on the management unit to determine a failed bit count of the management unit, and in response to the failed bit count of the management unit failing to satisfy a threshold criterion, remove the group of management units from the set of retired groups of management units.

A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device identifies a behavioral criterion associated with the data loss occurrence in the block of the memory component. The processing device further increments a counter associated with the block in response to an occurrence of the behavioral criterion, wherein a value of the counter corresponds to a number of occurrences of a plurality of behavioral criteria associated with data loss occurrences in the block. Responsive to determining that the value of the counter satisfies a first threshold criterion, the processing device designates the block as a quarantined block, performs a stress test of a plurality of stress tests of the block, and responsive to the block failing a first stress test, the processing device retires the block of the memory component.

A memory device includes a row decoder, a column decoder, and a repair control circuit, which is configured to: (i) compare a row address with a stored failed row address, (ii) compare a column address with a stored failed column address, (iii) control the row decoder to activate the at least one of a plurality of redundancy word lines when the row address corresponds to the failed row address, and (iv) control the column decoder to activate at least one of a plurality of redundancy bit lines when the column address corresponds to the failed column address. The repair control circuit varies a repair unit according to an address input during a repair operation.