The memory system comprising: a nonvolatile memory device including a plurality of memory blocks each including a plurality of pages, wherein the plurality of memory blocks include at least one bad block and normal block, and a controller suitable for performing a backup operation of copying data from an over-read page into a back-up page when the over-read page, a number of read requests to which is equal to or greater than a first reference number, is detected among the plurality of pages in the normal block, and reading the data from the back-up page in response to a read request for the over-read page after the backup operation, wherein the controller is further suitable for performing an operation of setting a page which is programmable/readable, among the plurality of pages in the bad block, as the back-up page.

A memory system includes a memory medium and a memory controller. The memory medium has a second address system that is different from a first address system of a host. The memory controller performs a control operation to access the memory medium based on a command from the host. The memory controller is configured to store a second address, corresponding to an address of a read data, when an error of the read data that is outputted from the memory medium is unrepairable and is configured to repair a region of the memory medium, designated by the second address, when the region of the memory medium that is designated by the second address is repairable.

A spin transfer torque magnetic random access memory (STT-MRAM) device according to the present embodiment comprises: an STT-MRAM memory array which includes a data storage unit for storing data, a defect area address storage unit for storing an address of a defect area, and a spare area for storing data of a failed area; and a bypass determination unit which includes a volatile information storage element for storing the address of the defect area, stored in the defect area address storage unit and provided thereto, and when memory array access occurs, compares an access address with the address of the defect area stored in the volatile information storage element and causes the memory array access to bypass to the spare area.

Devices, methods, and systems for managing temperature dependent failures in a memory device. An erase failure of a memory block is detected, and marked as a grown bad block if the memory device temperature is below a threshold temperature. If the temperature exceeds the threshold temperature, it is determined whether memory cells of the block exceed a first threshold voltage. If the memory cells of the block exceed the first threshold voltage, the block is marked as a potential grown bad block. If the memory cells of the block are below the first threshold voltage, it is determined whether a number of the memory cells of the block exceed a second threshold voltage. If the memory cells of the block are below the second threshold, the block is programmed. If the memory cells of the block exceed the second threshold, the block is marked for error correction and programmed.

Devices, methods, and systems for managing temperature dependent failures in a memory device. An erase failure of a memory block is detected, and marked as a grown bad block if the memory device temperature is below a threshold temperature. If the temperature exceeds the threshold temperature, it is determined whether memory cells of the block exceed a first threshold voltage. If the memory cells of the block exceed the first threshold voltage, the block is marked as a potential grown bad block. If the memory cells of the block are below the first threshold voltage, it is determined whether a number of the memory cells of the block exceed a second threshold voltage. If the memory cells of the block are below the second threshold, the block is programmed. If the memory cells of the block exceed the second threshold, the block is marked for error correction and programmed.

A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.

A nonvolatile memory includes a first sub-block defined by a first string select line and a first word line; a second sub-block defined by a second string select line different from the first string select line and a second word line different from the first word line; a first vacant block defined by the first string select line and the second word line; and a second vacant block defined by the second string select line and the first word line. First data is programmed in the first sub-block with, second data is programmed in the second sub-block, and no data is programmed in the first vacant block and the second vacant block.

A system includes a memory component, and a processing device coupled with the memory component. The processing device to identify a group of management units of the memory component, wherein the group of management units is included in a set of retired groups of management units, select a management unit from the group of management units, perform a media integrity check on the management unit to determine a failed bit count of the management unit, and in response to the failed bit count of the management unit failing to satisfy a threshold criterion, remove the group of management units from the set of retired groups of management units.

According to one embodiment, a memory system controls a plurality of parallel access units each of which includes a plurality of blocks belonging to the different nonvolatile memory chips. The memory system stores information indicating address conversion rules prescribed such that the number of defective blocks included in the parallel access units is equal to or smaller than a first number. Each of the address conversion rules indicates a mathematical rule for converting a block address to be sent to each of the nonvolatile memory chips into another block address. An address conversion circuit in the memory system converts each of block addresses to be sent to each nonvolatile memory chip into another block address, based on each mathematical rule.

Some examples described herein relate to redundancy in a multi-chip stacked device. An example described herein is a multi-chip device. The multi-chip device includes a chip stack including vertically stacked chips. Neighboring pairs of the chips are directly connected together. Each of two or more of the chips includes a processing integrated circuit. The chip stack is configurable to operate a subset of functionality of the processing integrated circuits of the two or more of the chips when any portion of the processing integrated circuits is defective.