A semiconductor memory apparatus includes a plurality of memory dies and a logic die, which are stacked to each other. The logic die includes a memory interface for a memory apparatus to be coupled to the semiconductor memory apparatus, and a switch coupled to a plurality of channels included in a control device which controls the semiconductor memory apparatus. The switch includes a first switch element which couples one of the plurality of channels to the memory interface or one of the plurality of memory dies, and a second switch element which couples another one of the plurality of channels to another one of the plurality of memory dies. Even if some memory dies are defective, the semiconductor memory apparatus is capable to operate.

A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.

Some examples described herein relate to redundancy in a multi-chip stacked device. An example described herein is a multi-chip device. The multi-chip device includes a chip stack including vertically stacked chips. Neighboring pairs of the chips are directly connected together. Each of two or more of the chips includes a processing integrated circuit. The chip stack is configurable to operate a subset of functionality of the processing integrated circuits of the two or more of the chips when any portion of the processing integrated circuits is defective.

A memory device is provided. The memory device includes a plurality of normal memory blocks; and at least two or more bad memory blocks, wherein data having the same number of bits as data to be stored in a normal memory block and a parity code having the number of bits at least twice greater than that of a parity code to be stored in the normal memory block are stored in a first bad memory block and a second bad memory block among the bad memory blocks.

A storage device includes a memory device configured to store program pulse information indicating whether the number of program pulses applied to selected memory cells during a program operation exceeds a reference value; and a memory controller configured to determine whether the probability of a growing defect occurring in the selected memory cells is present based on the program pulse information.

A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.

A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.

A nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory blocks, each including a plurality memory cells coupled to word-lines respectively, and the word-lines are stacked vertically on a substrate. The control circuit divides a first memory block of the plurality of memory blocks into a partial bad region and a partial normal region based on error information of an uncorrectable error of the first memory block which is designated as a bad block. The control circuit performs a memory operation on the partial normal region by applying a first bias condition to the partial bad region and by applying a second bias condition to the partial normal region, based on a command and an address, and the first bias condition is different from the second bias condition.

A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.

A partial memory die is removed from an edge of a wafer such that the partial memory die is missing a portion of the memory structure that was not printed on the wafer. A usable portion of the incomplete memory structure is determined and one or more rectangular zones in the usable portion of the incomplete memory structure are identified. During operation of the memory system, the memory system receives logical addresses for memory operations to be performed on the partial memory die and determines physical addresses that corresponding to the logical addresses. The memory system performs an out of bounds response for a physical address that is on the partial memory die but outside of the one or more rectangular zones. The memory system performs memory operations for physical addresses that are inside the one or more rectangular zones.