The present invention provides a sensitivity amplifier, its control method, a memory read-write circuit and a memory device. The sensitivity amplifier includes: a first PMOS transistor and a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, a first input/output terminal, and a second input/output terminal; four switch unit, the first PMOS and the first NMOS transistors are respectively connected to the first input/output terminal through one switch unit, the second PMOS and the second NMOS transistors are respectively connected to the second input/output terminal through another switch unit. The switch units configure each PMOS transistor and each NMOS transistor in an amplifier mode or in a diode mode. The first NMOS transistor's gate connects to the bit line, and the second NMOS transistor's gate connects to the reference bit line. The disclosed sensitivity amplifier has improved performance.

A semiconductor storage device includes a memory cell array having a plurality of memory cells connected to bit line pairs. At the time of data read from a memory cell, a replica bit line signal is output to a replica bit line in response to a replica word line signal, and a sense amplifier startup signal changes in response to the replica bit line signal whereby a sense amplifier is driven. At the time of data write into a memory cell, a low potential-side bit line of a write-target bit line pair is brought to a negative potential in response to a negative potential boost signal output from a negative potential generation circuit.

A semiconductor memory apparatus of the technology includes a current sink circuit configured to allow a portion of a current flowing through a memory cell to flow to a negative voltage terminal in a read operation and a sense amplifier configured to detect data of the memory cell and a detection result in response to a sense amplifier enable signal in the read operation. The current sink circuit varies an amount of the current flowing to the negative voltage terminal in response to the sense amplifier enable signal.

A semiconductor device includes a pull-up source voltage generation circuit configured to drive a pull-up voltage to a normal voltage during a normal period and to drive the pull-source voltage to a test voltage during a test period. The semiconductor device also includes a pull-down source voltage generation circuit configured to drive a pull-down voltage to a ground voltage during the normal period and to drive the pull-down source voltage to a bit line pre-charge voltage during the test period. The semiconductor device further includes an equalization control signal driver configured to receive the pull-up source voltage and the pull-down source voltage to drive an equalization control signal for equalizing voltage levels of an internal bit line pair of a bit line sense amplifier.

The present application provides a sense amplifier, a memory, and a control method. The sense amplifier includes: an amplification module, configured to: amplify a voltage difference between a bit line and a reference bit line; and a controlled power supply module, connected to the amplification module, and configured to: determine a drive parameter according to a first rated pull rate range and a second rated pull rate range, and supply power to the amplification module according to the drive parameter, to control the amplification module to pull a voltage of the bit line or a voltage of the reference bit line to a first preset value at a first rated pull rate at the amplification stage and pull the voltage of the reference bit line or the voltage of the bit line to a second preset value at a second rated pull rate at the amplification stage.

A semiconductor memory apparatus of the technology includes a current sink circuit configured to allow a portion of a current flowing through a memory cell to flow to a negative voltage terminal in a read operation and a sense amplifier configured to detect data of the memory cell and a detection result in response to a sense amplifier enable signal in the read operation. The current sink circuit varies an amount of the current flowing to the negative voltage terminal in response to the sense amplifier enable signal.

An improved method and apparatus for performing power management in a memory device is disclosed.

A semiconductor device includes a pull-up source voltage generation circuit configured to drive a pull-up voltage to a normal voltage during a normal period and to drive the pull-source voltage to a test voltage during a test period. The semiconductor device also includes a pull-down source voltage generation circuit configured to drive a pull-down voltage to a ground voltage during the normal period and to drive the pull-down source voltage to a bit line pre-charge voltage during the test period. The semiconductor device further includes an equalization control signal driver configured to receive the pull-up source voltage and the pull-down source voltage to drive an equalization control signal for equalizing voltage levels of an internal bit line pair of a bit line sense amplifier.

A semiconductor storage device includes a memory cell array having a plurality of memory cells connected to bit line pairs. At the time of data read from a memory cell, a replica bit line signal is output to a replica bit line in response to a replica word line signal, and a sense amplifier startup signal changes in response to the replica bit line signal whereby a sense amplifier is driven. At the time of data write into a memory cell, a low potential-side bit line of a write-target bit line pair is brought to a negative potential in response to a negative potential boost signal output from a negative potential generation circuit.