A memory device, a host device and a method of operating the memory device are provided. The memory device includes a data signal generator configured to provide a data signal to a transmission driver, the transmission driver configured to output a multi-level signal having any one of first to third signal levels based on the data signal, a command decoder configured to receive a feedback signal from outside of the memory device and decode the feedback signal, a data signal controller configured to adjust the data signal based on a decoding result of the command decoder, and a drive strength controller configured to adjust at least one of the first to third signal levels based on the decoding result of the command decoder.

Methods, systems, and devices for multi-driver signaling are described. An apparatus may include a first voltage source configured to supply a positive voltage and a second voltage source configured to supply a negative voltage. The apparatus may also include a first driver configured to couple a transmission line of a bus with the first voltage source and a second driver configured to couple the transmission line of the bus with the second voltage source. The first driver may be configured to transfer current to the transmission line based on a configurable resistance of the first driver. And the second driver configured to transfer current from the transmission line of the bus based on a configurable resistance of the second driver.

Methods, systems, and devices for buffer configurations for communications between memory dies and a host device are described. A memory device may include a buffer having a first interface coupled with a host device and a second interface coupled with a memory die of the memory device. The first interface may communicate information with the host device at a first frequency and according to a first signaling scheme, and the second interface may communicate information with the memory die at a second frequency and according to a second signaling scheme. The first frequency may be higher than the second frequency, and the second signaling scheme may include a greater quantity of voltage levels than the first signaling scheme.

Methods, systems, and devices for multi-driver signaling are described. An apparatus may include a first voltage source configured to supply a positive voltage and a second voltage source configured to supply a negative voltage. The apparatus may also include a first driver configured to couple a transmission line of a bus with the first voltage source and a second driver configured to couple the transmission line of the bus with the second voltage source. The first driver may be configured to transfer current to the transmission line based on a configurable resistance of the first driver. And the second driver configured to transfer current from the transmission line of the bus based on a configurable resistance of the second driver.

Methods, systems, and devices for buffer configurations for communications between memory dies and a host device are described. A memory device may include a buffer having a first interface coupled with a host device and a second interface coupled with a memory die of the memory device. The first interface may communicate information with the host device at a first frequency and according to a first signaling scheme, and the second interface may communicate information with the memory die at a second frequency and according to a second signaling scheme. The first frequency may be higher than the second frequency, and the second signaling scheme may include a greater quantity of voltage levels than the first signaling scheme.

A semiconductor device may include a page buffer comprising first to fifth latches, wherein the first to third latches and the fifth latch are configured to store 4-bit original data, among 5-bit original data, respectively, and the fourth latch is configured to store data identical with the data that has been stored in the second latch and a control circuit configured to determine a program inhibition pattern based on data that have been stored in two of the first to fifth latches and control the page buffer so that data that has been stored in at least one of the first to fifth latches is inverted based on the program inhibition pattern.

An encoder includes an encoding unit configured to receive 2n-bit read data and to generate 2m-bit read data, and an output driver configured to input m-bit first read data of the 2m-bit read data, to transmit voltage and/or current a first number of times corresponding to a number of first bits indicating a first state included in the m-bit first read data or to transmit current corresponding to the number of first bits during an activation period of a clock signal, and to transmit the voltage and/or the current a second number of times corresponding to a number of second bits indicating the first state included in m-bit second read data of the 2m-bit read data or to transmit current corresponding to the number of second bits during a deactivation period of the clock signal, wherein n is at least 2 and m is at least 3.

A method is disclosed herein which includes obtaining an array of analog memory elements. It also includes programming an analog memory element included in the array, where prior to being programmed the analog memory element has a first value for an electrical property, and where it is programmed to cause the analog memory element to perform a computation included in a series of computations performed by the array. Programming the analog memory element includes applying light or heat to the analog memory element, where a value of the electrical property is changed from the first value to a second value based upon application of light or heat to the analog memory element, and further where upon the value of the electrical property being changed from the first value to the second value, the analog memory element is configured to perform the computation responsive to receipt of an input.

This document describes apparatuses and techniques for implementing data masking with pulse amplitude modulation (PAM) encoded signals of a memory circuit. In various aspects, a data mask function of a memory controller may use an unassigned or prohibited PAM signaling state for a set of data lines to indicate data masking to a memory device for a group of data bits. For example, the data mask function may alter a PAM symbol or signal level for at least one data line from a low-voltage state (L) or mid-voltage state (M) state to a high-voltage state (H), resulting in a PAM signaling state for the set of data lines that corresponds data mask indication for the group of data bits. By so doing, the data mask function may indicate data masking for the group of bits without a dedicated data mask signal line, which may enable improved per-line memory bandwidth.

A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.