Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.

To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal. By subtracting the third current from a differential current between the fourth current and the fifth current, a current that depends on the sum of products of the first analog data and the second analog data is obtained.

To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal. By subtracting the third current from a differential current between the fourth current and the fifth current, a current that depends on the sum of products of the first analog data and the second analog data is obtained.

The present disclosure includes apparatuses and methods for data movement. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes a sense amplifier and a compute component coupled to a sense line and configured to implement operations. A controller in the memory device is configured to couple to the array and sensing circuitry. A shared I/O line in the memory device is configured to couple a source location to a destination location.

Systems and methods for securely sharing a memory between an Embedded Controller (EC) and a Platform Controller Hub (PCH). In some embodiments, an IHS may include: a chipset; a flash device coupled to the chipset; and an EC coupled to the flash device via a first bus and to the chipset via a second bus, wherein the EC comprises a Read-Only Memory (ROM) portion and a Random Access Memory (RAM) portion, the EC configured to: retrieve EC firmware from the flash device via the first bus; store the retrieved EC firmware in the RAM portion; and prior to the execution of any instruction stored in the RAM portion, relinquish access to the flash device via the first bus.

Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.

To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal. By subtracting the third current from a differential current between the fourth current and the fifth current, a current that depends on the sum of products of the first analog data and the second analog data is obtained.

In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal. By subtracting the third current from a differential current between the fourth current and the fifth current, a current that depends on the sum of products of the first analog data and the second analog data is obtained.

In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.