The present disclosure includes apparatuses and methods for data movement. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes a sense amplifier and a compute component coupled to a sense line and configured to implement operations. A controller in the memory device is configured to couple to the array and sensing circuitry. A shared I/O line in the memory device is configured to couple a source location and a destination location.

Techniques and mechanisms for providing data to be used in an in-memory computation at a memory device. In an embodiment a memory device comprises a first memory array and circuitry, coupled to the first memory array, to perform a data computation based on data stored at the first memory array. Prior to the computation, the first memory array receives the data from a second memory array of the memory device. The second memory array extends horizontally in parallel with, but is offset vertically from, the first memory array. In another embodiment, a single integrated circuit die includes both the first memory array and the second memory array.

Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.

The disclosed technology generally relates to magnetic devices, and more particularly to magnetic devices configured to generate a stream of domain walls propagating along an output magnetic bus. In an aspect, a magnetic device includes a magnetic propagation layer, which in turn includes a plurality of magnetic buses. The magnetic buses include an output magnetic bus configured to guide propagating magnetic domain walls. The magnetic propagation layer further comprises a central region in which the magnetic buses converge and are joined together. The magnetic buses include at least a first and a second magnetic bus having opposite magnetization orientations with respect to each other, such that a domain wall separating the opposite magnetization states is pinned in the central region. In another aspect, a method includes providing the magnetic device and generating the stream of domain walls propagating along the output magnetic bus by applying spin orbit and/or transfer torques to the pinned domain wall to alternate the pinned domain wall between two stable configurations, in which each stable configuration corresponds to a different magnetization state of the output magnetic bus in at least a region where the output magnetic bus is joined to the central region.

A resistive random-access memory (RRAM) system includes an RRAM cell. The RRAM cell includes a first select line and a second select line, a word line, a bit line, a first resistive memory device, a first switching device, a second resistive memory device, a second switching device, and a comparator. The first resistive memory device is coupled between a first access node and the bit line. The first switching device is coupled between the first select line and the first access node. The second resistive memory device is coupled between a second access node and the bit line. The second switching device is coupled between the second select line and the second access node. The comparator includes a first input coupled to the bit line, a second input, and an output.

A buffer device includes input lines, an input buffer unit and a remapping unit. The input lines are coupled to a memory and configured to be inputted with data from the memory in a current clock. The input buffer unit is coupled to the input lines and configured to buffer one part of the inputted data and output the part of the inputted data in a later clock. The remapping unit is coupled to the input lines and the input buffer unit, and configured to generate remap data for a convolution operation according to the data on the input lines and the output of the input buffer unit in the current clock. A convolution operation method for a data stream is also disclosed.

The present disclosure includes apparatuses and methods related to refresh in memory. An example apparatus can refresh an array of memory cells in response to a portion of memory cells in an array having threshold voltages that are greater than a reference voltage.

Examples of the present disclosure provide apparatuses and methods for determining a vector population count in a memory. An example method comprises determining, using sensing circuitry, a vector population count of a number of fixed length elements of a vector stored in a memory array.

The present disclosure includes apparatuses and methods related to refresh in memory. An apparatus can refresh an array of memory cells in response to a portion of memory cells in an array having threshold voltages that are greater than a reference voltage. The reference voltage can be determined by the threshold voltage being within a set margin of a second state.

The present disclosure includes apparatuses and methods related to refresh in memory. An apparatus can refresh an array of memory cells in response to a portion of memory cells in an array having threshold voltages that are greater than a reference voltage. The reference voltage can be determined by the threshold voltage being within a set margin of a second state.