A power management circuit in a low-power double data rate memory is configured to manage a plurality of power supplies memory according to a reference voltage. A low dropout regulator has a first transmitting terminal and a second transmitting terminal. The low dropout regulator adjusts a voltage difference between a first voltage and a second voltage according to the reference voltage. A power network structure is electrically connected to the low dropout regulator. A first power network circuit has a first connecting point, a grid shape and a first unit network space. A second power network circuit has a second connecting point, another grid shape and a second unit network space. The second connecting point is separated from the first connecting point by a distance. The distance is smaller than or equal to one of the first unit network space and the second unit network space.

A memory package includes a package substrate including a redistribution layer and bonding pads connected to the redistribution layer, the redistribution layer including a plurality of signal paths; a buffer chip mounted on the package substrate and including a plurality of chip pads corresponding to a plurality of memory channels; and a plurality of memory chips stacked on the package substrate and divided into a plurality of groups corresponding to the plurality of memory channels, wherein memory chips of a first group, among the plurality of memory chips, are connected to first chip pads of the plurality of chip pads through first wires, and wherein memory chips of a second group, among the plurality of memory chips, are connected to second chip pads of the plurality of chip pads through second wires and at least a portion of the plurality of signal paths.

A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.

A memory package includes; a first memory chip including first memory pads, and a buffer chip including first buffer pads respectively connected with the first memory pads and second buffer pads connected with an external device. The buffer chip respectively communicates signals received via the second buffer pads to the first buffer pads in response to a swap enable signal having a disabled state, and the buffer chip swaps signals received via the second buffer pads to generate first swapped signals, and respectively communicates the first swapped signals to the first buffer pads in response to the swap enable signal having an enabled state.

A memory device includes a first on-die termination circuit, a second on-die termination circuit, a voltage generator, and a code generator. The first on-die termination circuit may correspond to a data input buffer. The second on-die termination circuit may correspond to a command/address buffer. The voltage generator may generate a reference voltage. The code generator may generate a resistance calibration code of a selected one of the on-die termination circuits in response to the reference voltage. The reference calibration code may calibrate a resistance value of the selected on-die termination circuit.

A POR circuit includes a voltage divider coupleable between a supply voltage and a POR trace, including a first element coupled between the supply voltage and a node, and a second element coupled between the node and the POR trace. A switch is drain to source coupled between the POR trace and a reference voltage. A first decoupling capacitor is coupled between the POR trace and the reference voltage. A second decoupling capacitor is coupled between the node and the reference voltage. ESD protection for an integrated circuit includes charging a node of a voltage divider coupled between a supply voltage and a POR trace to a predetermined percentage of the supply voltage, decoupling high frequency noise with a first decoupling capacitor between the POR trace and a reference voltage, and decoupling low frequency noise with a second decoupling capacitor between the node and the reference voltage.

Apparatuses and techniques for operating devices with multiple differential write clock signals having different phases are described. For example, a memory controller (e.g., of a host device) can provide two differential write clock signals to a memory device over an interconnect. The two differential write clock signals may have a phase offset of approximately ninety degrees. Instead of generating its own phase-delayed write clock signals using a component (e.g., a clock divider circuit) that can enter the metastable state, the memory device can use the multiple differential write clocks signals provided by the memory controller to process memory requests.

A semiconductor device includes a substrate having an active cell region and an interfacial region adjacent to each other in a first direction, bit lines on the active cell region of the substrate that are spaced apart from each other in a second direction that intersects the first direction, and bit-line pads on the interfacial region of the substrate that are spaced apart from each other in the second direction. Each of the bit lines includes a first bit line and a second bit line that extend in the first direction and are spaced apart from each other in the second direction, a connection part that connects a first end of the first bit line to a second end of the second bit line, and a coupling part that connects one of the bit-line pads to one of the first bit line, the second bit line, and the connection part.

An operation method of a semiconductor device is disclosed. The semiconductor device includes separate first and second dies in a package and receives first types of signals through first and second respective channels independent of each other and corresponding to the first and second respective dies. The method includes a step in which when information for controlling internal operations of the first and second dies is first applied to the first die through a first pad, the first die performs the internal operation and also transmits the information to the second die through an internal interface connecting the first die and the second die, and a step in which when the information is transmitted to the second die, the second die performs the internal operation.

A hybrid memory system with improved bandwidth is disclosed. In one aspect, a memory system is provided that increases bandwidth relative to the JEDEC low-power double data rate version 5 (LPDDR5) standard. This improvement is made possible by increasing a data conductor count from sixteen to twenty-four. Optionally, the bandwidth may be further improved by increasing a clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complications of merely doubling pin counts or doubling clock speed. Further, coding techniques tailored to the pin count and pin layout are provided.