Disclosed herein is a method for designing a semiconductor device, the method including: assigning a plurality of wiring tracks including first and second tracks; connecting a first data I/O circuit to a first data node of a first circuit by a first signal bus arranged on the first wiring track; connecting a second data I/O circuit to a second data node of the first circuit by a second signal bus arranged on the second wiring track when a first design mode is selected; and connecting the first data I/O circuit to a second circuit by a second signal bus arranged on the second wiring track when a second design mode is selected.

Methods, systems, and devices for pin mapping for memory devices are described. An apparatus may include a memory array, a plurality of pins, a selector, and a mapping component. The memory array may include a plurality of data lines coupled with a plurality of memory cells. The mapping component may be configured to map a set of data lines to a first set of pins when the selector reflects a first state and to a second set of pins when the selector reflects a second state. The first and second set of pins may have a same quantity of pins. The second set of pins may include pins that are otherwise unused in the second state. The mapping component may be configured to selectively couple unused pins to a fixed potential.

Apparatuses, systems, and methods for faster memory access regions. A memory array may have a fiat bank which has a greater access speed than a second bank. For example the first bank may have a reduced read latency compared to the second bank. The first bank may have structural differences, such as reduced word line and/or reduced global input output (GIO) line length. In some embodiments, the first and second bank may have separate bank pad data buses, and data terminals. In some embodiments, they may share the bank pads data bus, and data terminals. In some embodiments, when an access command is received for the first (faster) bank while an access command to the second (slower) bank is still processing, the access to the faster bank may interrupt the access to the slower bank.

The invention provides a multi-die stacked package memory and an output synchronization method thereof. The multi-die stacked package memory includes multiple dies (100), and the multiple dies (100) are stacked and packaged together to form a stacked package structure. The multiple dies (100) share a CS #pin, and the CS #pin is configured to turn on or turn off the stacked package structure. The multiple dies (100) also share an IO pin. Each die (100) is provided with a SYNC_PAD pin. The SYNC_PAD pins of the multiple dies (100) are electrically connected together, the SYNC_PAD pins are configured to judge whether the multiple dies (100) are all in an idle status or not. The multi-die stacked package memory and the output synchronization method thereof are simple in structure, easy to realize, stable and reliable.

A memory device, and a method of operating the same, includes a plurality of pages, a peripheral circuit, and control logic. The peripheral circuit is configured to receive a command, an address, and data from an external controller to program a page selected from among the plurality of pages, and to generate internal input data depending on an input mode for the command, the address, and the data. The control logic is configured to determine whether internal input data is to be generated based on the data depending on the input mode and to control the peripheral circuit so that a program operation of programming the internal input data is performed.

A pseudo-dual-port memory (PDPM) is disclosed that includes a first memory array bank and a second memory array bank of a plurality of memory array banks. The PDPM also includes parallel pin control logic circuitry configured to perform operations including taking a clock signal, a memory enable signal for a first port, a memory enable signal for a second port, a parallel pin control signal, and address signals for the first and the second memory array banks as inputs and generating a first internal clock and a second internal clock for performing operations corresponding to the first and the second memory array banks at the first port and the second port. A total number of memory array banks may be up to eight memory array banks and each including either a six-transistors (6-T) SRAM bit-cell or an eight-transistors (8-T) SRAM bit-cell in static random access memory architecture.

Disclosed herein is an apparatus that includes a first power ESD protection circuit arranged in a first circuit area; a plurality of data I/O circuits arranged in a second circuit area adjacent to the first circuit area in a first direction; a plurality of data I/O terminals arranged in the second circuit area, each of the plurality of data I/O terminals being coupled to an associated one of the plurality of data I/O circuits; a plurality of first power terminals arranged in the second circuit area; and a first power line extending in the first direction, the first power line coupling the plurality of first power terminals to the first power ESD protection circuit.

Disclosed herein is an apparatus that includes a first power ESD protection circuit arranged in a first circuit area; a plurality of data I/O circuits arranged in a second circuit area adjacent to the first circuit area in a first direction; a plurality of data I/O terminals arranged in the second circuit area, each of the plurality of data I/O terminals being coupled to an associated one of the plurality of data I/O circuits; a plurality of first power terminals arranged in the second circuit area; and a first power line extending in the first direction, the first power line coupling the plurality of first power terminals to the first power ESD protection circuit.

A method of operating a memory macro includes receiving a first signal indicating a first operational mode of the memory macro, receiving a second signal indicating a second operational mode of the memory macro, generating, by a first logic circuit, a third signal and a fourth signal based on the first signal and a fifth signal thereby causing a change in the first operational mode of the memory macro, and generating, by a second logic circuit, the fifth signal and a sixth signal based on at least the second signal and thereby causing a change in the second operational mode of the memory macro. The first logic circuit is coupled to a first memory cell array and a first IO circuit. The second logic circuit is coupled to a first and second set of word line driver circuits.

An integrated-circuit memory component receives, as part of respective first and second memory read transactions, a first column access command that identifies a first volume of data and a second column read command that identifies a second volume of data, the second volume of data being constituted by not more than half as many data bits as the first volume of data. In response to receiving the first column access command, the integrated-circuit memory component transmits the first volume of data as N parallel bit-serial data signals over N external signaling links. In response to receiving the second column access command, the integrated-circuit memory component transmits the second volume of data as M parallel bit- serial data signals over M of the N external signaling links, where M is less than N.