A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.

Embodiments of operation methods of ferroelectric memory are disclosed. In an example, a method for reading ferroelectric memory cells is disclosed. The ferroelectric memory cells include a first set of ferroelectric memory cells and a second set of ferroelectric memory cells. In a first cycle, first data in a first ferroelectric memory cell of the first set of ferroelectric memory cells is sensed. In a second cycle subsequent to the first cycle, the sensed first data is written back to the first ferroelectric memory cell, and second data in a second ferroelectric memory cell of the second set of ferroelectric memory cells is simultaneously sensed.

A memory device comprises a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data, where N is a natural number, and a first peripheral circuit for controlling the first memory cells according to an N-bit data access scheme and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells according to an M-bit data access scheme and disposed below the second memory cell array, wherein the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight, wherein the plurality of first memory cells and the plurality of second memory cells are included in a first chip having a first metal pad, the first peripheral circuit and the second peripheral circuit are included in a second chip having a second metal pad, and the first chip and the second chip are vertically connected to each other by the first metal pad and the second metal pad.

Various implementations described herein refer to a method for providing single port memory with a bitcell array arranged in columns and rows. The method may include coupling a wordline to the single port memory including coupling the wordline to the columns of the bitcell array. The method may include performing multiple memory access operations concurrently in the single port memory including performing a read operation in one column of the bitcell array using the wordline while performing a write operation in another column of the bitcell array using the wordline, or performing a write operation in one column of the bitcell array using the wordline while performing a read operation in another column of the bitcell array using the same wordline.

Various implementations described herein refer to a method for providing single port memory with multiple different banks having a first bank and a second bank that is different than the first bank. The method may include coupling multiple wordlines to the single port memory including coupling a first wordline to the first bank and coupling a second wordline to the second bank. The method may include performing multiple memory access operations concurrently in the single port memory.

Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

A three-dimensional stacked integrated circuit (3D SIC) having a non-volatile memory die having an array of non-volatile memory partitions, a volatile memory die having an array of volatile memory partitions, and a processing logic die having an array of processing logic partitions. The non-volatile memory die, the volatile memory die, and the processing logic die are stacked. The non-volatile memory die, the volatile memory die, and the processing logic die can be arranged to form an array of functional blocks, and at least two functional blocks can each include a different data processing function that reduces the computation load of a controller.

A memory, a memory chip and a memory data access method are provided. The memory of the disclosure includes a plurality of memory chips. Each of the plurality of memory chips includes a first bank group, a second bank group and a read amplifier and a write amplifier. The first bank group includes a plurality of first memory banks. The second bank group includes a plurality of second memory banks. The read amplifier and the write amplifier are separately coupled to the first bank group and the second bank group. The read amplifier and the write amplifier are configured to independently access different bank groups.

Various implementations described herein are directed to a device having various circuitry for reading first data from a memory location in single-port memory and writing second data to the memory location in the single-port memory after reading the first data from the memory location. In some implementations, reading the first data and writing the second data to the memory location are performed in a single operation.