An apparatus has a controller and an array of memory cells, including a first section comprising a plurality of rows and a second section comprising a plurality of rows. The controller configured to, in association with wear leveling, transfer data stored in a first row of the first section from the first row to a register, transfer the data from the register to a destination row of the second section while data in a second row of the first section is being sensed.

Methods, systems, and devices related to data relocation via a cache are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In some cases, the memory device may transfer data from a first address of the memory array to the signal development cache. The memory device may transfer the data stored in the signal development cache to a second address of the memory array based on a parameter associated with the first address of the memory array satisfying a criterion for performing data relocation.

A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.

A memory controller with improved data reliability and a memory system including the same are provided, and an operating method of the memory controller includes, based on deterioration information indicating a location of a deterioration region in the plurality of blocks, with respect to data stored in a first block, copying user data of a RAID to a normal region other than the deterioration region of a second block; copying parity data of the RAID among the data stored in the first block to the deterioration region of the second block; and updating mapping information between data constituting one RAID and transmitting the mapping information to the memory device. The deterioration information includes information regarding one or more word lines at specific locations included in the deterioration region in the plurality of blocks.

A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.

A semiconductor device, semiconductor system, and or method relating to a refresh operation may be provided. The semiconductor device may include an operation control signal generation circuit configured for generating an operation control signal for a target word line. The semiconductor device may include a copy operation circuit configured for performing a first copy operation of storing data of first cells coupled to an adjacent word line adjacent to the target word line, in second cells coupled to a first clone word line, based on the operation control signal.

The present disclosure relates to a method for improving the reading and/or writing phase in storage devices including a plurality of non-volatile memory portions managed by a memory controller, comprising: providing at least a faster memory portion having a lower latency and higher throughput with respect to said non-volatile memory portions and being by-directionally connected to said controller; using said faster memory portion as a read and/or write cache memory for copying the content of memory regions including more frequently read or written logical blocks of said plurality of non-volatile memory portions.
A specific read cache architecture for a managed storage device is also disclosed to implement the above method.

A nonvolatile memory device includes a first area of single-level cells (SLCs) and a second area of multi-level cells (MLCs). The device determines whether a free block can be created by copying data between memory blocks of the first area. Upon determining that the free memory block can be created by copying data between the memory blocks of the first area, the device copies the data between the memory blocks of the first area to create the free memory block. Otherwise, the device selects at least one memory block from the first area and allocates the selected memory block as free memory block by copying the data stored in the selected memory block of the first area to the second area.

A storage device and a data storing method thereof are provided. The storage device includes a data storage medium and the control unit. The data storage medium includes a data storage area with a plurality of first type of data blocks. When a data reading operation is executed on a current data block of the data storage medium, the control unit determines whether a read count of the current data block is greater than a first threshold, determines whether the current data block is one of the first type of data blocks and generate a determination result according to the result, the control unit selects a plurality of first type of data blocks and switches the selected data blocks to a fast mode. Finally, the control unit moves data stored in the current data block to the selected data blocks under fast mode.

A memory device includes: memory cells; an operation mode determiner for determining any one of a normal operation mode and a memory communication operation mode of communicating data with another memory device; a pad control signal generator for generating a pad control signal for determining a pad to receive a signal corresponding to a data movement command of the memory controller according to the determined operation mode; a pad controller for receiving the signal through the determined pad according to the pad control signal; an internal command generator for generating an internal operation command corresponding to the data movement command according to the determined operation mode; and an operation controller for performing one of a read operation of reading first target data from the memory cells and a program operation of storing second target data in the memory cells, based on the internal operation command.