Data words to be written to a memory location are delta encoded in multi-write avoidance (MWA) code words. MWA code words result in no re-writing of single-bit storage cells containing logical 0's to a 0 state and no re-writing of logical 1's to cells that have already been written once to a logical 1. Potential MWA code words stored in a look-up table (LUT) are indexed by a difference word DELTA_D. DELTA_D represents a bitwise difference (delta) between a data word currently stored at the memory location and a new data word (NEW_D) to be stored at the memory location. Validation and selection logic chooses an MWA code word representing NEW_D to be written if the MWA code word does not violate the principle of multi-write avoidance. Some embodiments generate the MWA code words using a pattern generator rather than indexing the MWA code words from a LUT.

A non-volatile memory device has a charge pump for providing a programming current and an array of non-volatile memory cells. Each memory cell of the array is programmed by the programming current from the charge pump. The array of non-volatile memory cells is partitioned into a plurality of units, with each unit comprising a plurality of memory cells. An indicator memory cell is associated with each unit of non-volatile memory cells. A programming circuit programs the memory cells of each unit using the programming current, when fifty percent or less of the memory cells of each unit is to be programmed, and programs the inverse of the memory cells of each unit and the indicator memory cell associated with each unit, using the programming current, when more than fifty percent of the memory cells of each unit is to be programmed.

A method includes performing a memory operation at a magnetic tunnel junction (MTJ) storage element by, during a single memory clock cycle, reading a first value stored at the MTJ storage element, comparing the first value to a second value to be stored at the MTJ storage element, and selectively writing the second value to the MTJ storage element based on the comparison.

Providing for improved cell longevity for two-terminal memory devices is described herein. By way of example, wear leveling and management of array operations is provided to reduce an average number of set or reset cycles employed for programming new data to a two-terminal memory device. Reduction in set and reset cycles can facilitate reduced wear over time, increasing longevity of the memory device and enabling larger numbers of lifetime array operations. Wear leveling can comprise comparing existing data stored within a target set of memory cells, to new data to be written to the target cells, and changing only cells having different values between the existing and new data. In some examples, new data can be inverted to reduce a number of program or erase pulses required to program the new data over the existing data, among other examples of disclosed wear leveling.

Data words to be written to a memory location are delta encoded in multi-write avoidance (MWA) code words. MWA code words result in no re-writing of single-bit storage cells containing logical 0's to a 0 state and no re-writing of logical 1's to cells that have already been written once to a logical 1. Potential MWA code words stored in a look-up table (LUT) are indexed by a difference word DELTA_D. DELTA_D represents a bitwise difference (delta) between a data word currently stored at the memory location and a new data word (NEW_D) to be stored at the memory location. Validation and selection logic chooses an MWA code word representing NEW_D to be written if the MWA code word does not violate the principle of multi-write avoidance. Some embodiments generate the MWA code words using a pattern generator rather than indexing the MWA code words from a LUT.

Technology for writing data to a phase change memory array is disclosed. In an example, a method may include identifying mask logic for masking cells in the phase change memory array and routing the mask logic to the cells. The method may further include routing input data to the cells. Set and reset pulses for the cells may be selectively prevented or inhibited based on the mask logic.