In certain aspects, a method for operating a memory device is disclosed. The memory device includes a plurality of memory planes. Whether an instruction is an asynchronous multi-plane independent (AMPI) read instruction or a non-AMPI read instruction is determined. In response to the instruction being an AMPI read instruction, an AMPI read control signal is generated based on the AMPI read instruction, and the AMPI read control signal is directed to a corresponding memory plane of the memory planes. In response to the instruction being a non-AMPI read instruction, a non-AMPI read control signal is generated based on the non-AMPI read instruction, and the non-AMPI read control signal is directed to each memory plane of the memory planes.

Read reference levels are calibrated by calibrating integration times. An integration time is the length of time for which the charge on a sense node is allowed to change while the memory cell is being sensed. Calibrating the integration time is much faster than calibrating the reference voltage itself. This is due, in part, to reducing the number of different reference voltages that need to be applied during calibration. Calibrating the integration time may use different test integration times for a given read reference voltage, thereby reducing the number of read reference voltages. Hence, calibrating the integration time(s) is very efficient timewise. Also, power consumption may be reduced.

A non-volatile memory accelerator and a method for speeding up data access are provided. The non-volatile memory accelerator includes a data pre-fetching unit, a cache unit, and an access interface circuit. The data pre-fetching unit has a plurality of line buffers. One of the line buffers provides read data according to a read command, or the data pre-fetching unit reads at least one cache data as the read data according to the read command. The data pre-fetching unit further stores in at least one of the line buffers a plurality of pre-stored data with continuous addresses according to the read command. The cache unit stores the at least one cache data and the pre-stored data with the continuous addresses. The access interface circuit is configured to be an interface circuit of the non-volatile memory.

A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus in a memory device. The memory device includes a translation buffer chip, memory chips in independently selectable logical sub-ranks, a narrow external data bus to connect the translation buffer chip to a memory controller, and the wide internal data bus between the translation buffer chip and the memory chips. A data access is performed on only the first independently selectable logical sub-rank to access second data via the wide internal data bus. The example method also involves locating a first portion of the first data, a second portion of the first data, and the second data on the narrow external data bus during separate data transfers.

A method for reducing current consumption of a memory is disclosed, wherein the memory includes a controller and a plurality of banks, and each bank of the plurality of banks includes a plurality of segments. The method includes the controller enabling an activating command corresponding to a first row address and an address of a first bank of the plurality of banks; a word line switch of a segment of the first bank corresponding to the first row address being turned on according to the activating command; the controller enabling an access command corresponding to an address of the segment; a plurality of bit switches corresponding to the segment being turned on according to the access command; and the controller enabling a pre-charge command corresponding to an address of a following segment and the address of the first bank after the access command is disabled.

Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

A non-volatile memory device is provided. The non-volatile memory device includes a clock pin, a clock signal being received from a controller through the clock pin; a first input/output pin; a second input/output pin, data being received from the controller in synchronization with the clock signal through the second input/output pin; a command/address buffer configured to operate at a first operating speed and buffer a command and an address received through the first input/output pin in synchronization with the clock signal; a memory cell array including a plurality of memory cells; and a control logic configured to control operations with respect to the plurality of memory cells, based on the command and the address buffered in the command/address buffer.

A read-write conversion circuit includes: a read-write conversion module, performing a read-write operation in response to a read-write control signal to implement data transmission between each of a local data line, a local complementary data line, and a global data line, data signals of the local data line and data signals of the local complementary data line being opposite in phase during the read-write operation, and a control module, outputting a variable read-write control signal in response to a read-write speed configuration signal to control a speed of the read-write operation of the read-write conversion module to be variable.

An electronic device may include: a column control circuit configured to generate a column control pulse and a mode register enable signal, each with a pulse that is generated based on logic levels of a chip selection signal and a command address; and a control circuit configured to generate a read control signal to perform a read operation and a mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal and configured to generate a mode register control signal to perform the mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal.

The disclosure relates to a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory block including a plurality of memory strings, a pass circuit connected between local word lines of the memory block and global word lines and configured to connect the local word lines to the global word lines in response to a block selection signal, and a voltage providing circuit configured to generate an operation voltage during a program or read operation, apply the operation voltage to the global word lines, and discharge the global word lines when the program operation or the read operation is completed, and the pass circuit is configured to control the local word lines to be in a floating state after the program operation or the read operation is completed and before discharging the global word lines.