Embodiments relate to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. Reciprocal binary values may be written into the two memory cells that make up a memory pair. When activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. Embodiments are directed to writing and reading memory cell pairs.

A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

Numerous embodiments of analog neural memory arrays are disclosed. Two or more physical memory cells are grouped together to form a logical cell that stores one of N possible levels. Within each logical cell, the memory cells can be programmed using different mechanisms. For example, one or more of the memory cells in a logical cell can be programmed using a coarse programming mechanism, one or more of the memory cells can be programmed using a fine mechanism, and one or more of the memory cells can be programmed using a tuning mechanism. This achieves extreme programming accuracy and programming speed.

The present disclosure includes apparatuses and methods for cache operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The first subset is configured as a cache to perform operations on data moved from the second subset. The apparatus also includes a cache controller configured to direct a first movement of a data value from a subarray in the second subset to a subarray in the first subset.

Apparatuses and methods related to implementing refresh and access modes for memory. The refresh and access modes can be used to configure a portion of memory. The portions of memory can correspond to protected regions of memory. The refresh and access modes can influence the security level of data stored in the protected regions of memory.

The present disclosure includes apparatuses and methods for performing operations by a memory device in a self-refresh state. An example includes an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to direct performance of compute operations on data stored in the array when the array is in a self-refresh state.

The present disclosure includes apparatuses and methods to change data category values. An example is a memory device that includes an array having a plurality of sequences of memory cells, where each of the respective sequences of memory cells includes a plurality of designated subsets of memory cells, and the array includes a counter corresponding to one of the plurality of designated subsets of memory cells. The memory device is configured to receive input corresponding to a data batch, where the input includes a designation that corresponds to the one of the plurality of designated subsets of memory cells to be conditionally updated, and to change a numerical value stored by the counter corresponding to the one of the plurality of designated subsets of memory cells.

The present disclosure includes apparatuses and methods for performing operations by a memory device in a self-refresh state. An example includes an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to direct performance of compute operations on data stored in the array when the array is in a self-refresh state.

A static random access memory (SRAM) structure is provided. The structure includes a plurality of SRAM bit cells on a substrate. Each SRAM bit cell includes at least six transistors including at least two NMOS transistors and at least two PMOS transistors. Each of the at least six transistors being lateral transistors with channels formed from nano-sheets grown by epitaxy. The at least six transistors positioned in two decks in which a second deck is positioned vertically above a first deck relative to a working surface of the substrate, wherein at least one NMOS transistor and at least one PMOS transistor share a common vertical gate. A first inverter formed using a first transistor positioned in the first deck and a second transistor positioned in the second deck. A second inverter formed using a third transistor positioned in the first deck and a fourth transistor positioned in the second deck. A pass gate is located in either the first deck or the second deck.

A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. Each of the memory cells is coupled to one of the first search lines and one of the second search lines. The current sensing units, coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units.