A method includes sending a first signal from a memory device to a memory controller. The first signal indicates to the memory controller that particular memory cells of the memory device are to be refreshed by the memory device.

A semiconductor memory device includes: a memory cell array including a plurality of word lines; a word line driving unit suitable for activating a first word line among the plurality of word lines corresponding to an input address signal; an activation time detection unit suitable for enabling a detection signal by detecting an activation time of the first word line; an address latch unit suitable for latching an address information for a second word line corresponding to the first word line in response to the detection signal; and an address output unit suitable for providing the word line driving unit with the latched address information for the second word line during a refresh operation.

A semiconductor memory device includes: a memory cell array including a plurality of word lines; a word line driving unit suitable for activating a first word line among the plurality of word lines corresponding to an input address signal; an activation time detection unit suitable for enabling a detection signal by detecting an activation time of the first word line; an address latch unit suitable for latching an address information for a second word line corresponding to the first word line in response to the detection signal; and an address output unit suitable for providing the word line driving unit with the latched address information for the second word line during a refresh operation.

Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

An apparatus for adaptively adjusting refresh timing of a CIM based on eDRAM includes a replica array including a plurality of replica MAC arrays, each having replica cells arranged in a direction and number according to the direction and number in which memory cells performing MAC operations together in a CIM cell array are arranged and a refresh determination module that compares voltage levels of signals output from each of the plurality of replica MAC arrays with MAC operation results according to weights stored in replica cells of the plurality of replica MAC arrays and activates a refresh enable signal for refreshing memory cells of the CIM cell array.