Provided herein may be a memory system and a method of operating the memory system. The memory system may include: a semiconductor memory device including a plurality of memory cells to be programmed to an erase state and a plurality of program state; and a controller configured to control the semiconductor memory device to perform a program operation or a read operation in response to a request of a host. The controller may control the semiconductor memory device such that when, after a first program operation of the program operation has been performed, a number of program fail bits of the plurality of memory cells is greater than a maximum allowed number of ECC bits, a second program operation is performed on selected memory cells of the plurality of memory cells.

A memory device includes; a memory area including a first memory area including first memory cells storing N-bit data and a second memory area including second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.

A memory system includes a memory device, and a memory controller including a processor and an internal memory. A computer program including a neural network is stored in the memory system. The processor executes the computer program to extract a voltage level from each of a plurality of memory cells connected to one string select line (SSL), in which the memory cells and the SSL are included in a memory block of the memory device, provide the voltage levels as input to the neural network, and perform noise cancellation on the SSL, using the neural network, by changing at least one of the voltage levels from a first voltage level to a second voltage level. The first voltage level is classified into a first cluster of memory cells, and the second voltage level is classified into a second cluster of memory cells different from the first cluster.

Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network. In one embodiment, a method comprises receiving an input voltage, multiplying the input voltage by a coefficient to generate an output voltage, applying the output voltage to a gate of a selected memory cell, performing a sense operating using the selected memory cell and a reference device to determine a value stored in the selected memory cell, wherein a slope of a current-voltage characteristic curve of the reference device and a slope of the current-voltage characteristic curve of the selected memory cell are approximately equal during the sense operation.

According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first blocks including a memory cell capable of storing data of one bit, a second block including a memory cell capable of storing data of two or more bits. The semiconductor memory stores first data in a first latch circuit, and second data in a second latch circuit, and writes the first data into one of the first blocks in page units, and the second data into one of the first blocks in page units. The semiconductor memory writes data of at least two pages into the second block, using the first data stored in the first latch circuit and the second data stored in the second latch circuit.

A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.

According to one embodiment, a memory system includes: a semiconductor memory including a memory cell array, the memory cell array including a memory cell, and a controller configured to issue a first read command sequence after a lapse of a first time period from access to the semiconductor memory, and issue a second read command sequence after a lapse of a second time period from access to the semiconductor memory. When the controller issues the first read command sequence, the semiconductor memory applies a first voltage and a second voltage to the memory cell. When the controller issues the second read command sequence, the semiconductor memory applies a third voltage and a fourth voltage to the memory cell.

A nonvolatile memory device including: a memory cell array, the memory cell array including a plurality of cell strings, at least one of the cell strings including a plurality of memory cells stacked in a direction perpendicular to a surface of a substrate, at least one of the memory cells is a multi-level cell storing at least three bits; and a control logic circuit configured to control a page buffer to read a fast read page of the memory cells with one read voltage and at least two normal read pages of the memory cells with the same number of read voltages.

According to an embodiment, a control circuitry performing: a first operation of reading data out of a memory cell with a first voltage applied to a word line while changing the first voltage by a first shift amount within a first range, and a second operation of reading data out of the memory cell with a second voltage applied to the word line while changing the second voltage by a second shift amount within a second range, wherein the second shift amount is smaller than the first shift amount, and wherein the control circuitry performs the second operation to apply the second voltage to the word line subsequently to application of the first voltage to the word line in the first operation.

A computer-implemented method for writing to a printed memory device is disclosed. The computer-implemented method includes determining, by a microcontroller, a first encoding scheme from among a plurality of encoding schemes to write a first data portion from among a plurality of data portions, wherein the first encoding scheme comprises a first voltage and a first pulse width to be used to write the first data portion; providing, by the microcontroller, the first encoding scheme to an application-specific integrated circuit (ASIC); selecting, by the ASIC, a first target memory cell of the printed memory device corresponding to a first word line and a first bit line for the first data portion to be written; and writing, by the ASIC, the first data portion to the first target memory cell using the first encoding scheme.