Provided is a microswitch including a first electrode, a second electrode, and a porous coordination polymer conductor, in which the porous coordination polymer conductor is represented by the following Formula (1), and a metal forming the first electrode and a metal forming the second electrode have different oxidation-reduction potentials,

[ML.sub.x].sub.n(D).sub.y  (1),

where M represents a metal ion selected from group 2 to group 13 elements in a periodic table, L represents a ligand that has two or more functional groups capable of coordination to M in a structure of L and is crosslinkable with two M's, D represents a conductivity aid that includes no metal element, x represents 0.5 to 4 and y represents 0.0001 to 20 with respect to x as 1, n represents the number of repeating units of a constituent unit represented by [ML.sub.x], and n represents 5 or more.

Various embodiments of the present disclosure are directed towards a memory cell including a first ferromagnetic layer and a second ferromagnetic layer. A bottom electrode via overlies a substrate. A bottom electrode overlies the bottom electrode via. A data storage layer overlies the bottom electrode. The first ferromagnetic layer overlies the data storage layer and has a first magnetization pointing in a first direction. The second ferromagnetic layer overlies the bottom electrode via and has a second magnetization pointing in a second direction orthogonal to the first direct.

A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

Various embodiments of the present disclosure are directed towards a memory cell including a first ferromagnetic layer and a second ferromagnetic layer. A bottom electrode via overlies a substrate. A bottom electrode overlies the bottom electrode via. A data storage layer overlies the bottom electrode. The first ferromagnetic layer overlies the data storage layer and has a first magnetization pointing in a first direction. The second ferromagnetic layer overlies the bottom electrode via and has a second magnetization pointing in a second direction orthogonal to the first direct

Electrical switching technologies employ the otherwise undesirable line defect in crystalline materials to form conductive filaments. A switching cell includes a crystalline layer disposed between an active electrode and another electrode. The crystalline layer has at least one channel, such as a line defect, extending from one surface of the crystalline layer to the other surface. Upon application of a voltage on the two electrodes, the active electrode provides metal ions that can migrate from the active electrode to the other electrode along the line defect, thereby forming a conductive filament. The switching cell can precisely locate the conductive filament within the line defect and increase the device-to-device switching uniformity.

Technologies relating to improving LRS data retention and reliability in RRAM-based crossbar array circuits are disclosed. An example apparatus includes: a bottom electrode; a filament forming layer formed on the bottom electrode; and a top electrode formed on the filament forming layer. The filament forming layer is configured to form a filament within the filament forming layer responsive a switching voltage being applied to the filament forming layer. The filament forming layer may be made of one of the following materials: HfOxSiy, HfOxNy, HfOxAly, HfOx doped with SiO2, HfOx doped with Al2O3, HfOx doped with N, HfOx doped with Si.sub.3N.sub.4, HfOx doped with AlN, or a combination thereof. The bottom electrode or the top electrode may be made of one of the following materials: Pt, Ti, TiN, Pd, Ir, W, Ta, Hf, Nb, V, Ru, TaN, NbN, a combination therefore, or an alloy with other electrically conductive materials.

Aspects of the subject disclosure may include, for example, applying a setting voltage across first and second electrodes, wherein a nanowire with a first electrical resistance is electrically connected between the first and second electrodes, wherein the applying of the setting voltage causes a migration of ions from the first and/or second electrodes to a surface of the nanowire, and wherein the migration of ions effectuates a reduction of electrical resistance of the nanowire from the first electrical resistance to a second electrical resistance that is lower than the first electrical resistance; and applying a reading voltage across the pair of electrodes, wherein the reading voltage is less than the setting voltage, and wherein the reading voltage is sufficiently small such that the applying of the reading voltage causes no more than an insignificant change of the electrical resistance of the nanowire from the second electrical resistance. Other embodiments are disclosed.

Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.

A stacked resistive random access memory (ReRAM) structure is provided. The stacked ReRAM structure includes a channel, a ReRAM cell sub-structure and a contact via sub-structure. The ReRAM cell structure includes ReRAM cell, drain, gate and source layers, which are insulated from one another and respectively disposed in operative contact with the channel. The contact via sub-structures includes first, second, third and fourth contact vias, which are separate from one another. The first contact via is disposed in exclusive operative contact with the ReRAM cell layer. The second contact via is disposed in exclusive operative contact with the drain layer. The third contact via is disposed in exclusive operative contact with the gate layer. The fourth contact via is disposed in exclusive operative contact with the source layer.

A stacked resistive random access memory (ReRAM) structure is provided. The stacked ReRAM structure includes a channel, a ReRAM cell sub-structure and a contact via sub-structure. The ReRAM cell structure includes ReRAM cell, drain, gate and source layers, which are insulated from one another and respectively disposed in operative contact with the channel. The contact via sub-structures includes first, second, third and fourth contact vias, which are separate from one another. The first contact via is disposed in exclusive operative contact with the ReRAM cell layer. The second contact via is disposed in exclusive operative contact with the drain layer. The third contact via is disposed in exclusive operative contact with the gate layer. The fourth contact via is disposed in exclusive operative contact with the source layer.