Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.

A memory device is disclosed. The memory device includes a bottom contact. The memory device also includes a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure, where a first contact formed at an interface between the bottom contact and the memory layer is ohmic, and where a second contact formed at an interface between the memory layer and the top electrode is ohmic.

A memory device is disclosed. The memory device includes a bottom contact, and a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a lateral barrier layer connected to the bottom contact, the memory layer, and the conductive top electrode, where the lateral barrier layer is configured to substantially prevent conduction of ions or vacancies from the bottom contact, the memory layer, and the conductive top electrode to the lateral barrier layer.

A memory device including a template layer is disclosed. The memory device also includes a memory layer connected to the template layer, where the memory layer has a variable resistance, and where the crystalline structure of the memory layer matches the crystalline structure of the template layer. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure.

Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.

Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.

A memory device including a template layer is disclosed. The memory device also includes a memory layer connected to the template layer, where the memory layer has a variable resistance, and where the crystalline structure of the memory layer matches the crystalline structure of the template layer. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure.

A switching resistor has a low resistance state and a high resistance state. The switching resistor comprises a dielectric layer disposed between a first electrode and a second electrode. The switching resistor further comprises a textured boundary surface between the first electrode and the dielectric layer. The textured boundary surface promotes the formation of a conductive pathway in the dielectric layer between the first electrode and the second electrode.

Methods, systems, and devices for memory cells with asymmetrical electrode interfaces are described. A memory cell with asymmetrical electrode interfaces may mitigate shorts in adjacent word lines, which may be leveraged for accurately reading a stored value of the memory cell. The memory device may include a self-selecting memory component with a top surface area in contact with a top electrode and a bottom surface area in contact with a bottom electrode, where the top surface area in contact with the top electrode is a different size than the bottom surface area in contact with the bottom electrode.

A memory device including a template layer is disclosed. The memory device also includes a memory layer connected to the template layer, where the memory layer has a variable resistance, and where the crystalline structure of the memory layer matches the crystalline structure of the template layer. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure.