The present disclosure includes apparatuses, methods, and systems for sensing two memory cells to determine multiple data values. An embodiment includes a memory having a plurality of memory cells and circuitry configured to sense memory states of each of two self-selecting multi-level memory cells (MLC) of the plurality of memory cells to determine multiple data values. The data values are determined by sensing a memory state of a first MLC using a first sensing voltage in a sense window between a first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to a second memory state and sensing a memory state of a second MLC using a second sensing voltage in a sense window between the first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to the second memory state. The sequence of determining data values includes sensing the memory state of the first and the second MLCs using higher sensing voltages than the first and the second sensing voltages in subsequent sensing windows, in repeated iterations, until the state of the first and the second MLCs are determined. The first and second sensing voltages are selectably closer in the sense window to the first threshold voltage distribution or the second threshold voltage distribution.

A neuro-bionic device based on a two-dimensional Ti.sub.3C.sub.2 material is provided. The device includes a Pt/Ti/SiO.sub.2/Si substrate, a neuro-bionic layer formed on a Pt film layer of the Pt/Ti/SiO.sub.2/Si substrate, and an Al electrode layer formed on the neuro-bionic layer. The neuro-bionic layer is made of a two-dimensional Ti.sub.3C.sub.2 material. The neuro-bionic device of the present invention is prepared by an evaporating coating method and a drop-coating method. The preparation process is relatively simple. The prepared device can successfully simulate the characteristics of synapse. More importantly, the resistance of the device can be modulated continuously under a scanning of a pulse sequence with pulse width and interval of 10 ns, which is beneficial to the application of the device in the ultrafast synapse simulation.

Disclosed are a self-healing memory device including a lower electrode; a polymer nanocomposite layer formed on the lower electrode, wherein, when a structural defect occurs, the polymer nanocomposite layer repairs the structural defect and restores a memory function damaged due to the structural defect through a self-healing mechanism characterized by movement of a polymer material and hydrogen bonding; and an upper electrode formed on the polymer nanocomposite layer and a method of manufacturing the self-healing memory device.

A process is provided to trim PCRAM cells to have consistent programming curves. Initial programming curves of PCRAM cells are measured. A target programming curve is set up for the PCRAM cells. Each PCRAM cell is then modulated individually to meet the target programming curve.

A system may include an array of interconnected memristors. Each memristor may include a first electrode, a second electrode, and a memristor material positioned between the first electrode and the second electrode. The system may further include a controller communicatively coupled to the array of interconnected memristors. The controller may be configured to tune the array of interconnected memristors.

A projected memory device includes a carbon-based projection component. The device includes two electrodes, a memory segment, and a projection component. The projection component and the memory segment form a dual element that connects the two electrodes. The projection component extends parallel to and in contact with the memory segment. The memory segment includes a resistive memory material, while the projection component includes a thin film of non-insulating material that essentially comprises carbon. In a particular implementation, the non-insulating material and the projection component essentially comprises amorphous carbon. Using carbon and, in particular, amorphous carbon, as a main component of the projection component, allows unprecedented flexibility to be achieved when tuning the electrical resistance of the projection component.

A lead-free metallic halide memristor is disclosed. The lead-free metallic halide memristor comprises a first electrode layer, an active layer and a second electrode layer, of which the active layer is made of a metallic halide material. Experimental data have proved that the lead-free metallic halide memristor possesses synaptic plasticity because of showing characteristics of short-term potentiation, short-term depression, long-term potentiation, long-term depression during the experiments. Therefore, the lead-free metallic halide memristor has significant potential for being used as an artificial synaptic element so as to be further applied in the manufacture of a reservoir computing chip. Moreover, experimental data have also proved that the lead-free metallic halide memristor also shows the characteristics of multi-level resistive switching, whereupon the lead-free metallic halide memristor can be further used as analog non-volatile memory so as to be further applied in the manufacture of a neuromorphic computing chip.

Provided herein may be an electronic device. The electronic device may include a crossbar array including a plurality of first memory cells, a plurality of second memory cells, a plurality of row lines, a plurality of first column lines and a second column line, and a plurality of analog-to-digital converters respectively coupled to the plurality of first column lines, each of the plurality of analog-to-digital converters receiving a reference voltage. Each of the plurality of analog-to-digital converters determines a maximum value allowed to the analog signal voltage based on the reference voltage.

A resistive random-access memory (RRAM) circuit includes an RRAM device configured to output a cell current responsive to a bit line voltage, and a current limiter including an input terminal coupled to the RRAM device, first and second parallel current paths configured to conduct the cell current between the input terminal and a reference voltage node, and an amplifier configured to generate a first signal responsive to a voltage level at the input terminal and a reference voltage level. Each of the first and second current paths includes a switching device configured to selectively conduct a portion of the cell current responsive to the first signal.

According to one embodiment, a method for manufacturing a memory system that has memory cells with a variable resistance element and a switching element connected between a first wire and second wire, includes forming the variable resistance elements in the memory system in a low resistance state or a high resistance state, and then bringing each of the variable resistance elements into the low resistance state before performing either of a read operation or a write operation by performing an external initialization process that is different from the read operation and the write operation. In some examples, the variable resistance element can be a magnetoresistance type element and the external initialization process may be exposing the memory cells to an external magnetic field.