A circuit comprising an input, a ground, a first switch, a second switch and a bi-polar memristor, wherein the first switch is a first transistor and a gate of the first transistor is connected to a line to instruct setting of the bi-polar memristor, and the second switch is a second transistor and a gate of the second transistor is connected to a line to instruct re-setting of the bi-polar memristor.

Broadly speaking, embodiments of the present techniques provide an amplification circuit comprising a sense amplifier and at least one Correlated Electron Switch (CES) configured to provide a signal to the sense amplifier. The sense amplifier outputs an amplified version of the input signal depending on the signal provided by the CES element. The signal provided by the CES element depends on the state of the CES material. The CES element provides a stable impedance to the sense amplifier, which may improve the reliability of reading data from the bit line, and reduce the number of errors introduced during the reading.

A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.

Programmable interposers for connecting integrated circuits, methods for programming programmable interposers, and integrated circuit packaging are provided. The programmable interposers are electrically reconfigurable to allow custom system-in-package (SiP) operation and configuration, field configurability, and functional obfuscation for secure integrated circuits fabricated in non-trusted environments. The programmable interposer includes, in one implementation, an interposer substrate and a programmable metallization cell (PMC) switch. The PMC switch is formed on the interposer substrate and is coupled between a signal input and a signal output. The PMC switch is electrically configurable between a high resistance state and a low resistance state.

Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.

In an example, a method may include comparing input data to stored data stored in a memory cell and determining whether the input data matches the stored data based on whether the memory cell snaps back in response to an applied voltage differential across the memory cell.

Methods, systems, and devices related to 3D self-selecting-memory array of memory cells are described. The method relates to a solution for improving the fault-tolerant capability of memory devices, including: applying a triple-modular-redundancy calculation in a programming phase of the memory cells of a memory array, and adopting a sequence of two opposite dual polarity algorithms applied along a selected bit line and in parallel on the at least three selected word lines of the memory array.

In one example in accordance with the present disclosure a method of determining a state of a memristor in a crossbar array is described. In the method a bias voltage is applied to a target row line in the crossbar array, which bias voltage causes a bias current to pass through a target memristor along the target row line. The bias voltage is increased by a predetermined amount to a state voltage. A state current flowing through the target memristor is determined. The state current is based on the state voltage. A state of the target memristor is determined based on the state current.

According to one embodiment, a memory arrangement is described a memory including a memory cell and a sense amplifier coupled to the memory cell having a node whose potential depends on the difference between a current through the memory cell and a reference current, a detection circuit configured to generate a signal representing whether the current through the memory cell is above or below the reference current based on the potential of the node and a limitation circuit configured to receive the signal and to limit the change of the potential of the node caused by the difference between the current through the memory cell and the reference current in response to the signal.

According to one embodiment, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode, and includes a metal film and a resistance change film. The control circuit applies a voltage between the first electrode and the second electrode to transition a resistive state of the memory cell. The control circuit performs a first reset operation by applying a first pulse having a voltage of a first polarity to the memory cell, and applying a second pulse having a voltage of a second polarity that is an inverse of the first polarity to the memory cell after applying the first pulse.