Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F.sup.2.

A resistance-switchable material containing: an insulating support; and a complementary resistance switchable filler dispersed in the insulating support, wherein the complementary resistance switchable filler has a spherical core-shell structure containing: a spherical conductive core containing a conductive material; and an insulating shell formed on the surface of the core and containing an insulating material. The resistance-switchable material is capable of exhibiting complementary resistive switching characteristics with improved reliability and stability as symmetrical uniform filament current paths are formed in respective resistive layers adjacent to two electrodes with the conductive core of the complementary resistance-switchable filler at the center due to the electric field control effect by the spherical complementary resistance-switchable filler.

Disclosed are systems and methods for performing efficient vector-matrix multiplication using a sparsely-connected conductance matrix and analog mixed signal (AMS) techniques. Metal electrodes are sparsely connected using coaxial nanowires. Each electrode can be used as an input/output node or neuron in a neural network layer. Neural network synapses are created by random connections provided by coaxial nanowires. A subset of the metal electrodes can be used to receive a vector of input voltages and the complementary subset of the metal electrodes can be used to read output currents. The output currents are the result of vector-matrix multiplication of the vector of input voltages with the sparsely-connected matrix of conductances.

Disclosed are systems and methods for performing efficient vector-matrix multiplication using a sparsely-connected conductance matrix and analog mixed signal (AMS) techniques. Metal electrodes are sparsely connected using coaxial nanowires. Each electrode can be used as an input/output node or neuron in a neural network layer. Neural network synapses are created by random connections provided by coaxial nanowires. A subset of the metal electrodes can be used to receive a vector of input voltages and the complementary subset of the metal electrodes can be used to read output currents. The output currents are the result of vector-matrix multiplication of the vector of input voltages with the sparsely-connected matrix of conductances.

Disclosed are systems and methods for performing efficient vector-matrix multiplication using a sparsely-connected conductance matrix and analog mixed signal (AMS) techniques. Metal electrodes are sparsely connected using coaxial nanowires. Each electrode can be used as an input/output node or neuron in a neural network layer. Neural network synapses are created by random connections provided by coaxial nanowires. A subset of the metal electrodes can be used to receive a vector of input voltages and the complementary subset of the metal electrodes can be used to read output currents. The output currents are the result of vector-matrix multiplication of the vector of input voltages with the sparsely-connected matrix of conductances.

Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.

Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2 F.sup.2.

Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F.sup.2.

A resistance-switchable material containing: an insulating support; and a complementary resistance switchable filler dispersed in the insulating support, wherein the complementary resistance switchable filler has a spherical core-shell structure containing: a spherical conductive core containing a conductive material; and an insulating shell formed on the surface of the core and containing an insulating material. The resistance-switchable material is capable of exhibiting complementary resistive switching characteristics with improved reliability and stability as symmetrical uniform filament current paths are formed in respective resistive layers adjacent to two electrodes with the conductive core of the complementary resistance-switchable filler at the center due to the electric field control effect by the spherical complementary resistance-switchable filler

Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F.sup.2.