Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-layer dielectric (ILD) layer above a substrate. An RRAM element is on the conductive interconnect, the RRAM element including a first electrode layer on the uppermost surface of the conductive interconnect. A resistance switching layer is on the first electrode layer, the resistance switching layer including a first metal oxide material layer on the first electrode layer, and a second metal oxide material layer on the first metal oxide material layer, the second metal oxide material layer including a metal species not included in the first metal oxide material layer. An oxygen exchange layer is on the second metal oxide material layer of the resistance switching layer. A second electrode layer is on the oxygen exchange layer.

The present invention provides a method for reading a current for processing analog information in a memory array for a synaptic device. To this end, the present invention provides a method for reading a memory array including a two-terminal switching material, including (a) selecting at least one cell by applying a voltage to the memory array and (b) simultaneously measuring the sum of currents from the at least one cell selected. The voltage applied to the at least one cell selected in operation (a) is higher than a voltage applied to at least one cell not selected while being within a range in which all of the selected at least one cell is not turned on.

Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

The invention provides a resistive memory with better area efficiency without degrading reliability, which includes an array area, word lines, a local source line, bit lines, and a shared source line. In the array area, memory cells are arranged in a matrix, and each memory cells includes a variable resistance element and an accessing transistor. The word lines extend in a row direction of the array area and are connected to the memory cells in the row direction. The local source line extends in a column direction of the array area. The bit lines extend in the column direction and are connected to first electrodes of the memory cells in the column direction. The shared source line is connected to the local source line. The shared source line extends in the row direction and is connected to second electrodes of the memory cells in the row direction.

An enhanced ferroelectric transistor may include Interface switching modulation (ISM) layers along with a ferroelectric layer in the gate of the transistor to increase a memory window while maintaining relatively low operating voltages. The enhanced ferroelectric transistor may be implemented as a memory device storing more than two bits of information in each memory cell. An enhanced ferroelectric tunnel junction device may include ISM layers and a ferroelectric layer to amplify the tunneling barriers in the device. The ISM layers may form material dipoles that add to the effect of ferroelectric dipoles in the ferroelectric material.

A composition of matter consisting primarily of a stabilizing element and a transition metal oxide, wherein the transition metal oxide is an anti-ferromagnetic Mott insulator with strong spin orbit interactions, and the composition of matter has a canted crystal structure.

Provided is a resetting method of a resistive random access memory (RRAM) including the following steps. A first resetting operation and a first verifying operation on the at least one resistive memory cell are performed. Whether to perform a second resetting operation according to a verifying result of the first verifying operation is determined. A second verifying operation is performed after the second resetting operation is determined to be performed and is finished. To determine whether to perform a healing resetting operation according to a verifying result of the second verifying operation, which comprises: performing the healing resetting operation when a verifying current of the second verifying operation is greater than a predetermined current, wherein a resetting voltage of the healing resetting operation is greater than a resetting voltage of the second resetting operation.

A non-volatile memory cell includes a bottom electrode, a top electrode having a conductive material, a resistive layer interposed between the bottom electrode and the top electrode, and side portions covering sides of the top electrode and the resistive layer. The side portions contain an oxide of the conductive material. The non-volatile memory cell further includes a contact wire disposed on the top electrode. A width of the contact wire is less than a width between lateral outer surfaces of the side portions.

Provided is a resistive random access memory (RRAM) including at least one memory cell. The at least one memory cell includes a top electrode, a bottom electrode, a data storage layer, an oxygen gettering layer, a first barrier layer, and an oxygen supplying layer. The data storage layer is disposed between the top electrode and the bottom electrode. The oxygen gettering layer is disposed between the data storage layer and the top electrode. The first barrier layer is disposed between the oxygen gettering layer and the data storage layer. The oxygen supplying layer is disposed between the oxygen gettering layer and the top electrode and/or between the oxygen gettering layer and the first barrier layer.

Aspects of the subject disclosure may include, for example, applying a setting voltage across first and second electrodes, wherein a nanowire with a first electrical resistance is electrically connected between the first and second electrodes, wherein the applying of the setting voltage causes a migration of ions from the first and/or second electrodes to a surface of the nanowire, and wherein the migration of ions effectuates a reduction of electrical resistance of the nanowire from the first electrical resistance to a second electrical resistance that is lower than the first electrical resistance; and applying a reading voltage across the pair of electrodes, wherein the reading voltage is less than the setting voltage, and wherein the reading voltage is sufficiently small such that the applying of the reading voltage causes no more than an insignificant change of the electrical resistance of the nanowire from the second electrical resistance. Other embodiments are disclosed.