A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

Aspects of the subject disclosure may include, for example, applying a setting voltage across first and second electrodes, wherein a nanowire with a first electrical resistance is electrically connected between the first and second electrodes, wherein the applying of the setting voltage causes a migration of ions from the first and/or second electrodes to a surface of the nanowire, and wherein the migration of ions effectuates a reduction of electrical resistance of the nanowire from the first electrical resistance to a second electrical resistance that is lower than the first electrical resistance; and applying a reading voltage across the pair of electrodes, wherein the reading voltage is less than the setting voltage, and wherein the reading voltage is sufficiently small such that the applying of the reading voltage causes no more than an insignificant change of the electrical resistance of the nanowire from the second electrical resistance. Other embodiments are disclosed.

A semiconductor memory device includes: first wirings; second wirings intersecting the first wirings; and memory cells. Each of the memory cells is respectively formed between one of the first wirings and one of the second wirings. In a set operation, a set pulse is supplied between one of the first wirings and one of the second wirings. In a reset operation, a reset pulse is supplied between one of the first wirings and one of the second wirings. In a first operation, a first pulse is supplied between one of the first wirings and one of the second wirings. the first pulse has an amplitude equal to or greater than the greater of an amplitude of the set pulse and an amplitude of the reset pulse and has a pulse width greater than a pulse width of the set pulse.

An electronic storage memory device is disclosed. The memory device includes a first conductive layer, and also includes a memory layer connected to the first conductive layer, where the memory layer has a variable resistance, and where no amorphous layer exists between the first conductive layer and the memory layer.

Embodiments of the invention provide a method of forming a crossbar array. The method includes forming conductive row electrode lines and forming conductive column electrode lines. The conductive column electrode lines form a plurality of crosspoints at intersections between the conductive row electrode lines and the conductive column electrode lines. An RSD is formed at each of the plurality of crosspoints, wherein the RSD includes a first terminal, a second terminal, an active region having a switchable conduction state, and a protuberant contact communicatively coupled to the first terminal. The protuberant contact communicatively couples the first terminal through a first barrier liner to a first one of the conductive row electrode lines. The protuberant contact can be positioned with respect to the first barrier liner such that the first barrier liner does not impact the switchable conduction state of the active region.

A RRAM array and its manufacturing method are provided. The RRAM array includes a substrate having an array region which has a first region and a second region. The RRAM array includes a bottom electrode layer on the substrate, an oxygen ion reservoir layer on the bottom electrode layer, a diffusion barrier layer on the oxygen ion reservoir layer, a resistance switching layer on the diffusion barrier layer, and a top electrode layer on the resistance switching layer. The diffusion barrier layer in the first region is different from the diffusion barrier layer in the second region.

Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a filament and one or more lateral regions including a doping material that are between a top region and a bottom region of the switching layer. The RRAM further includes a top electrode disposed above the switching layer.

A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described.

Memristive devices and methods for setting the resistance of a memristive device include a first mixed conducting layer formed from a first material having a resistance that changes depending on an ion concentration and having multiple coexisting phases from concentration-dependent metastability. A second metastable, mixed conducting layer is formed from the first material. A barrier layer between the first conductor layer and the second conductor layer is formed from a second mixed conducting material having a chemical potential that prevents thermal ion diffusion between the first and second layer. The barrier layer provides an electrical threshold, above which ions are transferred between the first and second layer and below which the resistance of the device is read.