According to one embodiment, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode, and includes a metal film and a resistance change film. The control circuit applies a voltage between the first electrode and the second electrode to transition a resistive state of the memory cell. The control circuit performs a first reset operation by applying a first pulse having a voltage of a first polarity to the memory cell, and applying a second pulse having a voltage of a second polarity that is an inverse of the first polarity to the memory cell after applying the first pulse.

A memory device may be provided, including first, second and third electrodes, first and second mask elements and a switching layer. The first mask element may be arranged over a portion of and laterally offset from the first electrode. The second electrode may be arranged over the first mask element. The second mask element may be arranged over the second electrode. The third electrode may be arranged over a portion of and laterally offset from the second mask element. The switching layer may be arranged between the first electrode and the third electrode, along a first side surface of the first mask element, a first side surface of the second electrode and a first side surface of the second mask element.

A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.

Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.

The disclosure concerns a resistive memory cell, including a stack of a selector, of a resistive element, and of a layer of phase-change material, the selector having no physical contact with the phase-change material. In one embodiment, the selector is an ovonic threshold switch formed on a conductive track of a metallization level.

A memory structure can include a memory cell and a first barrier layer having a maximum hydrogen diffusion coefficient of 1×10.sup.−17 cm.sup.2/s, said first barrier layer adjacent to the memory cell to minimize contaminant movement to or from the memory cell.

Provided are embodiments for method of fabricating a dual damascene crossbar array. The method includes forming a bottom electrode layer on a substrate and forming a first memory device on the bottom electrode layer. The method also includes forming a dual damascene structure on the first memory device, wherein the dual damascene structure includes a top electrode layer and a first via, wherein the first via is formed between the first memory device and the top electrode layer. Also provided are embodiments for the dual damascene crossbar and embodiments for disabling memory devices of the dual damascene crossbar array.

Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.

Described are CMOS-compatible protonic resistive devices (e.g., processing elements and/or memory elements). In embodiments, a protonic resistive memory can be formed from a proton-sensitive metal oxide channel where the concentration of protons intercalated inside the layer is controlled to modulate its conductivity. The protons can initially be supplied to the material stack by an implantation method. Irradiation techniques can be implemented to increase the concentration and conductivity of protons inside the materials. Some designs can put the active layer and reservoir in direct contact, creating an electrolyte-free device. Designs provide scalable solutions for full-scale Si-integration.

Embodiments of the present invention provide a computer system, a voltage resistance controlling apparatus, and a method that comprises at least two electrodes on proximal endpoints; a first layer disposed on the at least two electrodes, wherein the first layer is a made of a metal-oxide; a second layer disposed on the second layer, wherein the second first layer is made of an electrically conductive metal-oxide; a forming contact disposed on the second layer, wherein a combination of the forming contact disposed on the first layer disposed on the second layer operatively connects the at least two electrodes; and a computer system operatively connected to the forming contact, wherein the computer system is configured to apply a predetermined voltage to the first layer and the second layer respectively and display an overall resistance increase using a user interface.