A memristor memory device comprises a memristive memory cell, an input terminal, an output terminal, and a gate terminal. The input terminal and the output terminal are directly attached to the memristive memory cell, and the gate terminal is electrically isolated from the memristive memory cell. The gate terminal is configured for receiving an electrical signal for a volatile modulation of a conductance of the memristive memory cell, by which a correction of non-ideal conductance modulations of the memristor memory device is achieved.

A resistive memory cell includes a P-well region, an isolation structure, an N-well region, a first gate structure, a second gate structure, a first N-type doped region, a second N-type doped region, a third N-type doped region, a fourth N-type doped region, a word line, a bit line, a conductor line and a program line. The third N-type doped region, the fourth N-type doped region and the N-well region are collaboratively formed as an N-type merged region. The bit line is connected with the first N-type doped region. The word line is connected with a conductive layer of the first gate structure. The conductor line is connected with the second N-type doped region and a conductive layer of the second gate structure. The program line is connected with the N-type merged region.

An enhanced ferroelectric transistor may include Interface switching modulation (ISM) layers along with a ferroelectric layer in the gate of the transistor to increase a memory window while maintaining relatively low operating voltages. The enhanced ferroelectric transistor may be implemented as a memory device storing more than two bits of information in each memory cell. An enhanced ferroelectric tunnel junction device may include ISM layers and a ferroelectric layer to amplify the tunneling barriers in the device. The ISM layers may form material dipoles that add to the effect of ferroelectric dipoles in the ferroelectric material.

Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.

Resistive elements for PCM RPUs and techniques for fabrication thereof using trench depth pattering are provided. In one aspect, an RPU device includes: a first electrode; a second electrode; a heater; and a PCM disposed over the first electrode, the second electrode and the heater, wherein the heater includes a combination of a first material having a resistivity r1 and a second material having a resistivity r2, wherein r1>r2, and wherein only the first material is present beneath the PCM and forms a resistive heating element. A method of operating an RPU device is also provided.

A multiply-accumulate calculation device includes: a plurality of first multiple calculation elements configured to generate first output signals by multiplying a first input signal corresponding to an input value by a weight and output the first output signals; and an accumulate calculation unit configured to calculate a sum of the first output signals output from the plurality of first multiple calculation elements in a calculation period from a point in time at which transition to a steady state has occurred after transient responses caused by charging to parasitic capacitors of the plurality of first multiple calculation elements according to input of the first input signal to a point in time after transient responses caused by discharging from the parasitic capacitors of the plurality of first multiple calculation elements according to input of the first input signal have started to be generated.

A semiconductor device includes two-terminal memory devices characterized by a range of program voltages and a first capacitance, wherein the two-terminal memory devices are coupled in parallel between ground and a first common node, a first capacitor having a second capacitance, coupled between ground and a second common node, a voltage source configured to provide an input voltage lower than the range of program voltages, a first operational amplifier including an inverting input, a non-inverting input, and an output, wherein the non-inverting input is coupled to the first voltage source, wherein the inverting input is coupled to a third common node, and wherein the output is coupled to a fourth common node, a first resistance device coupled between the third common node and the fourth common node, and wherein the first common node is coupled to the second common node and the third common node.

In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.

A high efficiency embedded-artificial synaptic element includes a semiconductor substrate, a select transistor, a metal layer, a first memory transistor and a second memory transistor. The select transistor is disposed on the semiconductor substrate and includes a select gate structure, a drain region and a source region. The metal layer is connected to the drain region. The first memory transistor includes a first gate structure, a first electrode region and a first memristor. The second memory transistor includes a second gate structure, a second electrode region and a second memristor. The second electrode region and the first electrode region are connected to each other and form a connection region, which is connected to the metal layer. The first memristor is formed between the first gate structure and the connection region, and the second memristor is formed between the second gate structure and the connection region.

A memory device includes a field effect transistor and a variable-capacitance capacitor. A gate structure includes a gate dielectric and an intermediate electrode. The variable-capacitance capacitor includes a lower capacitor plate comprising the intermediate electrode, an upper capacitor plate comprising a control gate electrode, and a variable-capacitance node dielectric and including an electrical-field-programmable metal oxide material. The electrical-field-programmable metal oxide material provides a variable effective dielectric constant, and a data bit may be stored as a dielectric state of the variable-capacitance node dielectric in the memory device. The variable-capacitance node dielectric provides reversible electrical field-dependent resistivity modulation, or reversible electrical field-dependent movement of metal atoms therein.