A memory device includes at least one memory cell which contains a resistive memory element having a conductive metal oxide located between a first electrode and a second electrode. The conductive metal oxide has a concentration of free electrons in thermodynamic equilibrium in a range from 1.0×10.sup.20/cm.sup.3 to 1.0×10.sup.21/cm.sup.3. A method of operating the memory device includes redistributing electron density to set and reset the device. An oxide barrier layer may be located between the conductive metal oxide and the second electrode.

A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.

A single memory cell has the functions of a storage element and a selector. The memory cell includes a P-type layer, a tunneling structure and an N-type layer. The tunneling structure is formed on the P-type layer. The N-type layer is formed on the tunneling structure. The tunneling structure is a stack structure including a first material layer, a second material layer and a third material layer. By adjusting a bias voltage that is applied to the P-type layer and the N-type layer, the tunneling structure is controlled to be in the amorphous state or the crystalline state. Consequently, the memory cell has the memorizing and storing functions. The memory cell has the P-type layer, the tunneling structure and the N-type layer. By adjusting the bias voltage, the function of the selector is achieved.

According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrode; and a selector which selectively switches the heat supplied by the upper electrode and the lower electrode to the phase-change layer, wherein the selector is formed of a compound which includes a transition metal in the phase-change material so as to have a high resistance when the crystalline state of the selector is crystalline and so as to have a low resistance when the crystalline state of the selector is non-crystalline.

Various aspects relate to a threshold switch structure and a use of such threshold switch structure as a threshold switch in a memory cell arrangement, the threshold switch structure including: a first electrode, a second electrode, a switch element in direct physical contact with the first electrode and the second electrode, the switch element including a layer of a spontaneously polarizable material. The first electrode, the second electrode, and the switch element are configured to allow for a switching of the switch element between a first electrical conductance state and a second electrical conductance state as a function of a voltage drop provided over the switch element by the first electrode and the second electrode.

According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrode; and a selector which selectively switches the heat supplied by the upper electrode and the lower electrode to the phase-change layer, wherein the selector is formed of a compound which includes a transition metal in the phase-change material so as to have a high resistance when the crystalline state of the selector is crystalline and so as to have a low resistance when the crystalline state of the selector is non-crystalline.

A crested barrier memory device may include a first electrode, a first self- rectifying layer, and a combined barrier and active layer. The first self-rectifying layer may be between the first electrode and the active layer. A conduction band offset between the first self-rectifying layer and the combined barrier and active layer may be greater than approximately 1.5 eV. A valence band offset between the first self-rectifying layer and the combined barrier and active layer may be less than approximately −0.5 eV. The device may also include a second electrode. The active layer may be between the first self-rectifying layer and the second electrode.

According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrode; and a selector which selectively switches the heat supplied by the upper electrode and the lower electrode to the phase-change layer, wherein the selector is formed of a compound which includes a transition metal in the phase-change material so as to have a high resistance when the crystalline state of the selector is crystalline and so as to have a low resistance when the crystalline state of the selector is non-crystalline.

The present invention relates to a synapse and synaptic array, and a computing system using the same. The synaptic device according to an exemplary embodiment of the present invention includes a transistor in which a synaptic input signal is applied to any one electrode of source and drain electrodes; and a plurality of two-terminal variable resistance memory devices in which a first electrode is electrically globally connected to a gate electrode of the transistor, wherein a separate memory voltage is applied to a second electrode of each variable resistance memory device to adjust a gate voltage applied to the gate electrode, thereby controlling a synaptic output signal which is output to the other one of the source and drain electrodes.

A crested barrier memory and selector device may include a first electrode, a first self-rectifying, tunneling layer having a first dielectric constant, and an active, barrier layer that has a second dielectric constant and another self-rectifying, tunneling layer having a third dielectric constant. The first self-rectifying layer may be between the first electrode and the active layer. The second dielectric constant may be at least 1.5 times larger than the first dielectric constant. The device may also include a second electrode, where the active, barrier layer is between the first self-rectifying, tunneling layer and the second electrode.