A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.

A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.

According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrode; and a selector which selectively switches the heat supplied by the upper electrode and the lower electrode to the phase-change layer, wherein the selector is formed of a compound which includes a transition metal in the phase-change material so as to have a high resistance when the crystalline state of the selector is crystalline and so as to have a low resistance when the crystalline state of the selector is non-crystalline.

To accurately read data in a storage device provided with a cell having a variable resistance value. In a reference cell circuit, a resistance value changes to a predetermined initial value when an initialization signal exceeding a predetermined reversal threshold is input. A reference side signal source inputs a reference side read signal of a predetermined value not exceeding the predetermined reversal threshold to the reference cell circuit after the initialization signal is input to the reference cell circuit when there is an instruction to read with respect to a memory cell. A cell side signal source inputs a cell side read signal of the predetermined value to the memory cell after the initialization signal is input. A comparison unit compares a reference signal output from the reference cell circuit into which the reference side read signal has been input, and a cell signal output from the memory cell into which the cell side read current has been input, and acquires the comparison result as read data.

A device comprising a control unit and a plurality of resistive cells. The plurality of resistive cells each comprises a first terminal, a second terminal and a polymorphic layer comprising a polymorphic material. The polymorphic layer is configured to form a tunnel barrier. The polymorphic layer is arranged between the first terminal and the second terminal. The first terminal, the second terminal and the polymorphic layer form a tunnel junction.

A device comprising a control unit and a plurality of resistive cells. The plurality of resistive cells each comprises a first terminal, a second terminal and a polymorphic layer comprising a polymorphic material. The polymorphic layer is configured to form a tunnel barrier. The polymorphic layer is arranged between the first terminal and the second terminal. The first terminal, the second terminal and the polymorphic layer form a tunnel junction.

A resistive random access memory (Device) is disclosed. The Device includes a substrate, a first electrode formed atop the substrate, a tunneling barrier layer formed atop the first electrode, an active material formed atop the tunneling barrier layer, an isolation layer formed atop the active material, and a second electrode formed atop the isolation layer, the first electrode and the second electrode provide electrical connectivity to external components, where the active material is a phase change material which undergoes phase transition in the presence of an electric field, Joule heating, or a combination thereof.

A method of switching a phase-change device (Device), including changing phase of the Device from a semiconducting 2H phase to a new 2Hd phase with a higher conductivity, the Device having an active material with a thickness including a phase transition material to thereby transition the Device from a high resistive state (HRS) to a low resistive state (LRS) by application of a set voltage and further to return the Device from the LRS back to the HRS by application of a reset voltage.

A resistive random access memory (Device) is disclosed. The Device includes a substrate, a first electrode formed atop the substrate, a tunneling barrier layer formed atop the first electrode, an active material formed atop the tunneling barrier layer, an isolation layer formed atop the active material, and a second electrode formed atop the isolation layer, the first electrode and the second electrode provide electrical connectivity to external components, where the active material is a phase change material which undergoes phase transition in the presence of an electric field, Joule heating, or a combination thereof.

A ferroelectric memory device includes a first electrode layer disposed on a substrate, a first tunnel barrier layer disposed on the first electrode layer, a second electrode layer disposed on the first tunnel barrier layer, a second tunnel barrier layer disposed on the second electrode layer, and a third electrode layer disposed on the second tunnel barrier layer. Any one of the first and second tunnel barrier layers includes a ferroelectric material.