A read and write circuit of a three-dimensional phase-change memory including an operation control circuit and a read and write operation circuit connected to each other. The operation control circuit is configured to load a correct operation pulse onto the read and write operation circuit. A read and write unit in the read and write operation circuit is connected to a memory cell and is configured to load the correct operation pulse onto the memory cell corresponding to the three-dimensional phase-change memory and to mirror the correct operation pulse to a mirror current. A bandgap reference source and a hysteresis comparator are connected to a mirror circuit branch. A feedback chopper circuit loop is connected across the memory cell and the mirror circuit branch and is configured to monitor a current flowing through the memory cell in real time.

Methods, systems, and devices for techniques that support sidewall structures for memory cells in vertical structures are described. A memory cell may include a first electrode, a second electrode, and a self-selecting storage element between the first electrode and the second electrode. The self-selecting storage element may extend between the first electrode and the second electrode in a direction that is parallel with a plane defined by the substrate. The self-selecting storage element may also include a bulk region and a sidewall region. The bulk region may include a chalcogenide material having a first composition, and the sidewall region may include the chalcogenide material having a second composition that is different than the first composition. Also, the sidewall region may extend between the first electrode and the second electrode.

A method for forming a three-dimensional memory structure above a semiconductor substrate includes forming two or more active stack sections, each formed on top of each other and separated by a dielectric buffer layer, where each active stack section includes multilayers separated by isolation dielectric layers and trenches with shafts filled with a sacrificial material. After the multiple active stack sections are formed, the method removes the sacrificial material in the shafts and removes portions of the dielectric buffer layer between shafts of adjacent active stack sections. The method fills the openings with a gate dielectric layer and a gate conductor. In some embodiments, the gate dielectric layer is discontinuous in the shaft over the depth of the multiple active stack sections.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including a plurality of first transistors and at least one metal layer, where the at least one metal layer overlays the first single crystal layer, and where the at least one metal layer includes interconnects between the plurality of first transistors, the interconnects between the plurality of first transistors include forming first control circuits; a second level overlaying the at least one metal layer, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors, where the second level includes a plurality of first memory cells, the first memory cells each including at least one of the plurality of second transistors, where the third level includes a plurality of second memory cells, the second memory cells each including at least one of the plurality of third transistors, where at least one of the plurality of second memory cells is at least partially atop of the first control circuits, where the first control circuits are adapted to control data written to at least one of the plurality of second memory cells; and where the plurality of second transistors are horizontally oriented transistors.

A system may include a memory array for VMM and includes a matrix of devices. The devices may be configured to receive a programming signal to program a weight to store a matrix of weights. The devices may be configured to receive a digital signal representative of a vector of input bits. The devices may generate an analog output signal by individually multiplying input bits by a corresponding weight. The system may include multiple ADCs electrically coupled to a corresponding device. Each ADC may be configured to convert a corresponding analog output signal to a digital signal based on a current level of the corresponding analog output signal. The system may include registers electrically coupled to a corresponding ADC configured to shift and store an output vector of bits of a corresponding digital output signal based on an order of the vector of input bits received by the corresponding device.

A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.

According to one embodiment, a semiconductor memory device includes: a first and a second wirings; a third wiring disposed between them; a first phase change layer disposed between the first and the third wirings; a first conducting layer disposed on a first wiring side surface of the first phase change layer; a second conducting layer disposed on a third wiring side surface of the first phase change layer; a second phase change layer disposed between the third and the second wirings; a third conducting layer disposed on a third wiring side surface of the second phase change layer; and a fourth conducting layer disposed on a second wiring side surface of the second phase change layer. The first and the fourth conducting layers have coefficients of thermal conductivity larger or smaller than the coefficients of thermal conductivity of the second and the third conducting layers.

Methods, systems, and devices for restoring memory cell threshold voltages are described. A memory device may perform a write operation on a memory cell during which a logic state is stored at the memory cell. Upon detecting satisfaction of a condition, the memory device may perform a read refresh operation on the memory cell during which the threshold voltage of the memory cell may be modified. In some cases, the duration of the read refresh operation may be longer than the duration of a read operation performed by the memory device on the memory cell or on a different memory cell.

A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a gate line structure disposed over the substrate, a gate dielectric layer covering one sidewall surface of the gate line structure and disposed over the substrate, a channel layer disposed to cover the gate dielectric layer and disposed over the substrate, a bit line structure and a resistance change structure to contact different portions of the channel layer over the substrate, and a source line structure disposed in the resistance change structure. The gate line structure includes at least one gate electrode layer pattern and interlayer insulation layer pattern that are alternately stacked along a first direction perpendicular to the substrate, and extends in a second direction perpendicular to the first direction.

An example apparatus can include a memory array and a memory controller. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The memory controller can be coupled to the first portion and the second portion. The memory controller can be configured to operate the first plurality of memory cells for short-term memory operations. The memory controller can be further configured to operate the second plurality of memory cells for long-term memory operations.