An operation method for a memory device is provided. The memory device includes a two-terminal selector and a resistance variable storage element coupled to the two-terminal selector. The method includes providing a voltage pulse to the memory device. A voltage applied across the two-terminal selector during a falling part of the voltage pulse falls below a holding voltage of the two-terminal selector. A voltage falling rate of the falling part at which the voltage applied across the two-terminal selector reaches the holding voltage is raised for reducing threshold voltage drift of the two-terminal selector.

An in-memory computing architecture is disclosed that can evaluate the transitive closure of graphs using the natural parallel flow of information in 3-D nanoscale crossbars. The architecture can be implemented using 3-D crossbar architectures with as few as two layers of 1-diode 1-resistor (1D1R) interconnects. The architecture avoids memory-processor bottlenecks and can hence scale to large graphs. The approach leads to a runtime complexity of O(n.sup.2) using O(n.sup.2) memristor devices. This compares favorably to conventional algorithms with a time complexity of O((n.sup.3)/p+(n.sup.2) log p) on p processors. The approach takes advantage of the dynamics of 3-D crossbars not available on 2-D crossbars.

A DPE memristor crossbar array system includes a plurality of partitioned memristor crossbar arrays. Each of the plurality of partitioned memristor crossbar arrays includes a primary memristor crossbar array and a redundant memristor crossbar array. The redundant memristor crossbar array includes values that are mathematically related to values within the primary memristor crossbar array. In addition, the plurality of partitioned memristor crossbar arrays includes a block of shared analog circuits coupled to the plurality of partitioned memristor crossbar arrays. The block of shared analog circuits is to determine a dot product value of voltage values generated by at least one partitioned memristor crossbar array of the plurality of partitioned memristor crossbar arrays.

A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.

A memory device includes first to nth decks respectively coupled to first to nth row lines which are stacked over a substrate in a vertical direction perpendicular to a surface of the substrate, n being a positive integer, a first connection structure extending from the substrate in the vertical direction to be coupled to the first row line, even-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of even-numbered row lines among the second to nth row lines, and odd-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of odd-numbered row lines among the second to nth row lines. The even-numbered connection structures are spaced apart from the odd-numbered connection structures with the first row line and the first connection structure that are interposed between the even-numbered connection structures and the odd-numbered connection structures.

A method for manufacturing a nonvolatile semiconductor storage device includes: forming a first conductive layer by self-alignment on a first wiring layer, and performing an annealing processing; stacking a first stacked film on the first conductive layer; processing the first stacked film, the first conductive layer, and the first wiring layer into a stripe structure extending in a first direction; forming and planarizing a first interlayer insulating film; forming a second wiring layer; forming a second conductive layer by self-alignment on the second wiring layer, and performing an annealing processing; processing the second wiring layer and the second conductive layer into a stripe structure extending in a second direction intersecting the first direction; and processing the first stacked film and the first interlayer insulating film below and between the second wiring layer, and forming a first memory cell having the first stacked film in a columnar shape.

Three-dimensional vertical memory array cell structures and processes. In an exemplary embodiment, a 3D vertical memory array structure is formed by performing operations that include forming an array stack having alternating metal layers and insulator layers, forming a hole through the array stack to expose internal surfaces of the metal layers and internal surfaces of the insulator layers, and performing a metal-oxidation process on the internal surfaces of the metal layers to form selector devices on the internal surfaces of the metal layers. The operations also include depositing one of resistive material or phase-change material within the hole on the selector devices and the internal surfaces of the insulator layers, such that the hole is reduced to a smaller hole, and depositing conductor material in the smaller hole.

An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.

A memory device includes a memory cell array including memory cells connected to word lines and bit lines. Each of the memory cells includes a switch element and a memory element, and has a first state or a second state in which a threshold voltage is within a first voltage range or a second voltage range, lower than the first voltage range. A memory controller is configured to execute a first read operation for the memory cells using a first read voltage, higher than a median value of the first voltage range, program first defect memory cells turned off during the first read operation to the first state, execute a second read operation for the memory cells using a second read voltage, lower than a median value of the second voltage range, and execute a repair operation for second defect memory cells turned on during the second read operation.

Disclosed is a memory device for cancelling a sneak current. The memory device according to the exemplary embodiment of the present disclosure includes a memory cell array which includes a plurality of word lines and a plurality of bit lines intersecting each other and memory cells disposed at intersections of the word lines and the bit lines; and a sensing circuit which supplies a bit line current to all or some of the bit lines, cancels a sneak current based on the bit line current by at least one switching control, and senses and amplifies data stored in the memory cell to output the sensed and amplified data.