A memory includes first lines arrayed along a surface of a substrate. Second lines are arrayed along the surface of the substrate either above or below the first lines and intersecting with the first lines. Resistance change memory cells are provided to correspond to intersection regions between the first lines and the second lines, respectively. First switching elements are arranged on a side of first ends of the first lines and transmitting a first voltage for writing or reading data to at least one memory cell among the memory cells. Second switching elements are arranged on a side of second ends of the first lines on an opposite side to the first ends and transmitting the first voltage to at least another one memory cell among the memory cells. The first switching elements and the second switching elements are connected to different ones of the first lines, respectively.

An integrated circuit memory device includes a plurality of row selection transistors and a dummy row selection transistor, on a substrate. A plurality of word lines and a plurality of dummy word lines are also provided on the substrate. A plurality of memory cells are provided, which are electrically connected to corresponding ones of the plurality of word lines. A plurality of dummy memory cells are provided, which are electrically connected to corresponding ones of the plurality of dummy word lines. A first wiring structure is provided, which electrically connects a first one of the plurality of word lines to a first one of the plurality of row selection transistors, and a second wiring structure is provided, which electrically connects the plurality of dummy word lines together and to the dummy row selection transistor.

Techniques for controlling current through memory cells are disclosed. In the illustrative embodiment, control circuitry may receive an instruction to perform an operation on a memory cell. The control circuitry determines properties of an electrical path that includes the memory cell, such as the capacitance and resistance of the electrical path. The control circuitry determines any additional current that should be applied to the memory cell beyond a base current. The control circuitry can adjust a bias current signal to increase the current through the memory cell when performing the operation based on the electrical characteristics of the path through the memory cell.

A crossbar array apparatus suppressing deterioration of write precision due to a sneak current is provided. A synapse array apparatus includes a crossbar array configured by connecting resistance-variable type memory elements, a row selecting/driving circuit, a column selecting/driving circuit, and a writing unit performing a write operation to a selected resistance-variable type memory element. The writing unit measures the sneak current generated when applying a write voltage to a selected row line before applying the write voltage, and then the writing unit performs the write operation to the selected resistance-variable type memory element by applying a write voltage having a sum of the measured sneak current and a current generated for performing the write operation.

According to the embodiment, in a first period, the semiconductor storage device maintains the switch in an ON state. In a second period, the semiconductor storage device performs a first operation, a second operation and a third operation while maintaining the switch in an OFF state. The second period is a period after the first period. The first operation is an operation to supply the first pulse having the first polarity from the first pulse generation circuit to the other end of the first capacitive element. The second operation is an operation to supply the second pulse having the second polarity from the second pulse generation circuit to the other end of the second capacitive element. The third operation is an operation to connect the first bit line to the first data line.

A variable resistance memory device includes: a memory cell including a first and second sub memory cell; and a first, second and third conductor. The first sub memory cell is above the first conductor, and includes a first variable resistance element and a first bidirectional switching element. The second sub memory cell is above the second conductor, and includes a second variable resistance element and a second bidirectional switching element. The second conductor is above the first sub memory cell. The third conductor is above the second sub memory cell. The variable resistance memory device is configured to receive first data and to write the first data to the memory cell when the first data does not match second data read from the memory cell.

Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.

Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.

A non-volatile memory device of the disclosure includes a memory cell, a writing circuit, and a current controller. The memory cell is disposed at an intersection of a first wiring and a second wiring, and includes a variable resistance element having a resistance state that is variable between a first resistance state and a second resistance state. The writing circuit varies the variable resistance element from the first resistance state to the second resistance state, and thereby performs writing of data on the memory cell. The current controller controls a current and thereby limits the current to a predetermined limit current value. The current is caused to flow through the first wiring or the second wiring by the writing circuit upon performing of the writing of the data. The current controller causes the predetermined limit current value to be a first limit current value in a period before a time at which the variable resistance element is varied to the second resistance state, and varies the predetermined limit current value from the first limit current value to a second limit current value after the time at which the variable resistance element is varied to the second resistance state.

A memory includes first signal-lines divided into groups. Global signal lines correspond to the first signal-lines. The global signal-lines include a selected global signal-line and a non-selected global signal-line. First transistors correspond to the first signal-lines. The first transistors are connected between a corresponding first signal-line and any of the global signal-lines. Selection signal-lines correspond to the groups. The selection signal-lines are connected to gate electrodes of the first transistors included in a corresponding group. Second transistors are connected between the first signal-lines that belong to adjacent two of the groups. When one of the first signal-lines which is electrically connected to the selected global signal-line is a selected first signal-line, the first transistors corresponding to one of the groups which includes the selected first signal-line is in a conducting state. One of the second transistors which is connected to the selected first signal-line is in a non-conducting state.