A nonvolatile memory device includes a resistance switching layer, a gate on the resistance switching layer, a gate oxide layer between the resistance switching layer and the gate, and a source and a drain, spaced apart from each other, on the resistance switching layer. A resistance value of the resistance switching layer is changed based on an illumination of light irradiated onto the resistance switching layer and is maintained as a changed resistance value.

A semiconductor memory device has a NOR-type memory cell array, a crossbar array, an entry gate, and a column selecting/signal processing unit. The crossbar array has a plurality of rows and columns, variable resistor elements formed in intersections of rows and columns respectively. The entry gate arranged between the memory cell array and the crossbar array, connects a selected bit line of the memory cell array to the crossbar array based on a selection signal. The column selecting/signal processing unit has a column writing unit, a column reading unit, and a NOR writing unit. The column writing unit writes data read from the memory cell array to a selected column of the crossbar array. The column reading unit reads data of the selected column of the crossbar array. The NOR writing unit at least writes data read by the column writing unit to the memory cell array.

In one embodiment, a state is encoded into a memory cell comprising a phase change material (PM) region and a select device (SD) region by: applying a first current in the memory cell over a first time period, wherein the first current applied over the first time period causes the PM region of the memory cell to be placed into an amorphous state and the SD region of the memory cell to be placed into an amorphous state; and applying a second current in the memory cell over a second time period after the first time period, wherein the second current applied over the third time period causes the SD region of the memory cell to be placed into a crystalline state and the PM region of the memory cell to remain in the amorphous state.

A memristor crossbar array (MCA) circuit includes an input processor configured to receive an input signal corresponding to a predetermined number of input values and to apply the input signal to memristors arranged along input lines, an MCA including the memristors having resistance values based on at least one transformation matrix including binary element values, and an outputter configured to output a frequency component intensity of the input signal based on a signal that is output from each of output lines on which the memristors are arranged, in response to the input signal being applied to the memristors.

A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.

A memory device enabling a reduced minimal conductance state may be provided. The device comprises a first electrode, a second electrode and phase-change material between the first electrode and the second electrode, wherein the phase-change material enables a plurality of conductivity states depending on the ratio between a crystalline and an amorphous phase of the phase-change material. The memory device comprises additionally a projection layer portion in a region between the first electrode and the second electrode. Thereby, an area directly covered by the phase-change material in the amorphous phase in a reset state of the memory device is larger than an area of the projection layer portion oriented to the phase-change material, such that a discontinuity in the conductance states of the memory device is created and a reduced minimal conductance state of the memory device in a reset state is enabled.

Provided herein may be an electronic device. The electronic device may include a crossbar array including a plurality of first memory cells, a plurality of second memory cells, a plurality of row lines, a plurality of first column lines and a second column line, and a plurality of analog-to-digital converters respectively coupled to the plurality of first column lines, each of the plurality of analog-to-digital converters receiving a reference voltage. Each of the plurality of analog-to-digital converters determines a maximum value allowed to the analog signal voltage based on the reference voltage.

The present disclosure relates to a logic operation circuit for computation in memory, which comprises an equivalent circuit input terminal, a reference circuit input terminal, a reset input terminal and an output terminal; wherein the equivalent circuit input terminal is configured to input the equivalent voltage of a memory computing array, the reset input terminal is configured to input a reset voltage, and the reference circuit input terminal is configured to input a reference voltage; the logic operation circuit for computation in memory outputs different output voltages according to the difference between the equivalent voltage and the reference voltage, and the output voltage is output through the output terminal; the logic operation circuit of the present disclosure has a simple structure, reduced complexity and effectively saved resources.

Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

Systems, methods, and apparatus to evaluate read margin when reading memory cells in a memory device. In one approach, a controller of a memory device applies an initial read voltage of an initial polarity to memory cells. Errors from the read are used to determine whether read retry is needed. If so, a pre-read voltage of an opposite polarity is applied, and errors determined. Based on the errors from applying the pre-read voltage, a polarity is selected for the read retry voltage. The read retry voltage of the selected polarity is then applied to the memory cells.