Provided in one example is an article. The article including: a first electrode; a switching layer disposed over at least a portion of the first electrode, the switching layer including a metal oxide; and a second electrode disposed over at least a portion of the switching layer. The first electrode, the switching layer, and the second electrode are parts of a resistive random-access memory, and one or both of the first electrode and the second electrode is a part of a layer of a printed circuit board.

The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (V.sub.REF) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on V.sub.REF and a detected memory cell voltage V.sub.LWL.

Resistive RAM (RRAM) devices having increased uniformity and related manufacturing methods are described. Greater uniformity of performance across an entire chip that includes larger numbers of RRAM cells can be achieved by uniformly creating enhanced channels in the switching layers through the use of radiation damage. The radiation, according to various described embodiments, can be in the form of ions, electromagnetic photons, neutral particles, electrons, and ultrasound.

A method to access two memory cells include determining a first cell current flowing through a first memory cell by subtracting a sneak current associated with the first memory cell from a first access current of the first bitline and determining a second cell current flowing through a second memory cell in the first bitline or a second bitline by subtracting the sneak current associated with the first memory cell from a second access current of the first bitline or the second bitline.

A resistive memory apparatus may include a memory region including a plurality of resistive memory cells arranged in a plurality of memory cell pairs. The resistive memory apparatus may include a voltage generating circuit configured to generate a read voltage code based on a switching state of at least one memory cell pair. The resistive memory apparatus may include a voltage providing unit configured to generate a read voltage corresponding to the read voltage code.

A nonvolatile memory device includes a nonvolatile memory cell and a variable resistive load portion. The variable resistive load portion is coupled between a bit line of the nonvolatile memory cell and a supply voltage line. The variable resistive load portion is suitable for changing a resistance value between the bit line and the supply voltage line according to a level of a supply voltage applied to the supply voltage line.

The invention is directed to a device for high-dimensional encoding of a plurality of sequences of quantitative data signals. The device comprises a plurality of input channels for receiving the plurality of sequences of quantitative data signals and an encoding unit. The encoding unit is configured to perform a temporal high-dimensional encoding of n-grams of the plurality of sequences of quantitative data signals; thereby creating a plurality of temporally encoded hypervectors for the plurality of input channels. The encoding unit is further configured to perform a spatial high-dimensional encoding of the plurality of temporally encoded hypervectors, thereby creating a temporally and spatially encoded hypervector. The device further comprises a configuration controller. The configuration controller is adapted to configure the high-dimensional encoding in dependence on one or more hyperparameter values.

Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.

In an example, a method may include comparing input data to stored data stored in a memory cell and determining whether the input data matches the stored data based on whether the memory cell snaps back in response to an applied voltage differential across the memory cell.

A semiconductor memory device according to an embodiment includes a memory cell array that includes a plurality of memory cells. The memory cell array comprises: a plurality of first conductive layers that are stacked in a first direction above a substrate and extend in a second direction intersecting the first direction; a second conductive layer extending in the first direction; a variable resistance film provided at intersections of the plurality of first conductive layers and the second conductive layer; a first select transistor disposed closer to a side of the substrate than a lowermost layer of the plurality of first conductive layers, the first select transistor including a first select gate line intersecting the second conductive layer; a third conductive layer that extends in a third direction intersecting the second direction and is connected to a lower end of the second conductive layer via the first select transistor; and a second select transistor disposed between at least one pair of the plurality of first conductive layers adjacent in the first direction, the second select transistor including a second select gate line intersecting the second conductive layer.