A system for generating images on a test and measurement device includes a first input for accepting a waveform input signal carrying sequential digital information and an image generator structured to generate a visual image using a segment of the waveform input only when two or more sequential codes of digital information match sequential codes carried in the sequential digital information of the segment of the waveform input. A user-defined state-machine comparator may be used to determine which segments of the waveform input signal are used in the image generation.

Methods and systems for collecting operational data from a target digital system are disclosed. In some embodiments, a method includes determining a test configuration to be used to configure a probe circuit. Determining the test configuration may include selecting one or more signal sources, defining one or more signal patterns within the selected signal sources, and defining one or more trigger events associated with the one or more signal patterns. Based on the test configuration, the probe circuit selects input/output (I/O) channels for a test cycle and captures one or more traces from the selected I/O channels during the test cycle.

Improved determination of a trigger time. For this purpose, an input signal is provided to multiple low pass filters having different bandwidths. A trigger event is detected in each of the low pass filtered signals and a corresponding trigger time is determined. The trigger time which is determined based on valid trigger detection and provided by the low pass filter with the highest bandwidth is used for further analysis.

The invention relates to a signal analyzer, comprising a signal receiving unit configured to receive a signal, in particular a radio frequency (RF) signal, a digitizing unit configured to digitize the received signal, and a trigger detection unit configured to detect a trigger event in the digitized signal. The signal analyzer further comprises an acquisition unit configured to store a segment of the digitized signal in a memory of the signal analyzer if the trigger detection unit detects the trigger event in the digitized signal, and an anomaly search unit configured to analyze the stored segment of the digitized signal in order to detect signal anomalies, in particular glitches, in the stored segment of the digitized signal.

An improved zooming for a representation of a measurement signal is provided. Two views for an acquired measurement signal are generated. A first view provides an overview of the acquired measurement signal, and a second view provides a horizontally zoomed section of the acquired measurement signal. The zoom window of the zoomed view is automatically set such that a predetermined number of periods are covered by the zoomed view.

An oscilloscope includes an input port to receive an input signal, a trigger system coupled to the input port and operable to generate a trigger signal in response to detecting a trigger event in the input signal, the trigger system includes at least one finite state machine, and a snippet compiler configured to accept one or more Declarative Trigger Language (DTL) code snippets as an input, compile the one or more DTL code snippets into one or more state machine op codes, and output the one or more state machine op codes. The trigger system uses the one or more state machine op codes to configure the at least one finite state machine.

An acquisition system includes a first acquisition and quantizer unit, a second acquisition and quantizer unit as well as a trigger unit. The first and second acquisition and quantizer units are configured to receive a respective interleaved digitized input signal, to acquire the respective interleaved digitized input signal, to quantize the respective interleaved digitized input signal, and to output a respective quantized interleaved digitized input signal. The trigger unit is configured to receive the respective quantized interleaved digitized input signals from the first and second acquisition and quantizer units. The trigger unit is further configured to de-interleave the respective quantized interleaved digitized input signals. The trigger unit is configured to generate a de-interleaved quantized digitized input signal. The trigger unit is also configured to detect an event in the de-interleaved quantized digitized input signal. Further, a method of acquiring a high bandwidth input signal is described.

A multilevel triggering system includes a trigger block library configured to store multiple triggering function modules for performing triggering functions to detect corresponding triggering conditions, respectively; and a triggering matrix including multiple triggering levels, each triggering level being configurable to include one or more trigger blocks and each trigger block being configurable to implement a triggering function module of the multiple triggering function modules, each trigger block generating a corresponding block trigger when the corresponding triggering condition of the triggering function module implemented by the trigger block is detected in a portion of an input signal. Each triggering level is configured to generate a corresponding level trigger when each of the one or more trigger blocks in the triggering level generates the corresponding block trigger. The triggering matrix is configured to generate a complex trigger signal when the triggering levels generate corresponding level triggers.

A circuit and a method for reducing interference of power on/off to hardware test. The circuit includes: a power unit, a voltage processing unit, a PSU and a to-be-tested hardware. An input terminal of the voltage processing unit is connected to the power unit, an output terminal of the voltage processing unit is connected to an input terminal of the PSU, and an output terminal of the PSU is connected to the to-be-tested hardware; the power unit is configured to provide an operating voltage; the voltage processing unit is configured to eliminate electric sparks caused by instability of the operating voltage at an instant of power on/off; the PSU is configured to convert a stable operating voltage outputted from the voltage processing unit into a direct current voltage required for the to-be-tested hardware; and the to-be-tested hardware is configured to receive the direct current voltage outputted from the PSU.

A system includes a plurality of oscilloscopes, each oscilloscope having an output port and an input port, a cable connecting the output port of an initial oscilloscope of the plurality of oscilloscopes to the input port of a second oscilloscope of the plurality of oscilloscopes, the initial oscilloscope having a processing element to generate a master run clock, the second oscilloscope having a processing element including a phase-locked loop to lock a slave run clock to the master run clock, wherein the processing element of one of the oscilloscopes executes code to cause the processing element to manipulate one of the run clocks to pass trigger information to another of the plurality of oscilloscopes. A method of synchronizing at least two oscilloscopes including a master oscilloscope and at least one slave oscilloscope includes connecting the at least two oscilloscopes together using output ports and input ports of the at least two oscilloscopes and at least one cable; sending a master run clock from the master oscilloscope to at least one slave oscilloscope; synchronizing a run clock of the at least one slave oscilloscope to the master run clock; recognizing a trigger event at a first oscilloscope of the at least two oscilloscopes; altering the run clock at the first oscilloscope to encode a trigger indication; and receiving the altered run clock at a second oscilloscope of the at least two oscilloscopes, wherein the trigger indication causes the second oscilloscope to recognize the trigger event.