A method of detecting whether a receiver coil is near a transmit coil in a wireless power transfer system (WPTS), the method involving: applying a pseudo-random signal to the transmit coil; while the pseudo-random signal is being applied to the transmit coil, recording one or more signals produced within the WPTS in response to the applied pseudo-random signal; by using the one or more recorded signals, generating a dynamic system model for some aspect of the WPTS; and using the generated dynamic system model in combination with stored training data to determine whether an object having characteristics distinguishing the object as a receiver coil is near the transmit coil.

A state change feature value relating to power supply current waveform data is extracted, and a transition state is detected, for a section of the waveform data, based on a magnitude of a state change feature value extracted.

An electrocardiogram (ECG) signal processing system is provided. The ECG signal processing system comprises an analog-to-digital converter (ADC) configured to convert an input analog ECG signal into a digital ECG signal, and a digital signal processing engine (DSPE) coupled to the ADC to receive the digital ECG signal. The DSPE is configured to decompose and reconstruct the digital ECG signal. A dynamic system clock source is coupled to the ADC and the DSPE for dynamic signal sampling, the dynamic system clock source clocking the ADC and the DSPE at a first frequency f1 to detect one or more first parameters of the input analog ECG signal and at a second frequency f2 to detect one or more second parameters of the input analog ECG signal.

An electrical test and measurement device is described that has at least one analog channel comprising an analog input, an attenuator circuit, an amplifier unit, and a digitizer. The electrical test and measurement device comprises another digitizer allocated to a digitizer input of the electrical test and measurement device. The digitizer input is configured to be connected to a measurement extension device. Further, a measurement extension device and a test and measurement system are described.

Sampling for arc-fault detection, ground-fault detection, and grounded-neutral fault detection uses a single analog-to-digital converter (ADC). The arc-fault and ground-fault sampling occurs at regular sampling periods that are relatively short com pared to the time between them, thus allowing grounded-neutral fault sampling to occur before and/or after one of these sampling periods. A predefined event may be used to ensure the grounded-neutral fault sampling occurs immediately before and/or after one of the periodic sampling periods. The predefined event may be the expiration of a timer or the time for a sinusoidal signal in a ground fault sense circuit to make a predefined number of zero-crossings. This avoids interference between the arc-fault sampling, the ground-fault sampling and grounded-neutral fault sampling, allowing a single ADC to perform all samplings concurrently. The timing of the predefined event may be periodically reset to compensate for any changes due to temperature and/or over time.

A first phasor measurement data can be received. The first phasor measurement data can be generated by a measurement of at least a first phasor parameter of a utility power as received by a first data center. At least a second phasor measurement can be received. The second phasor measurement can be generated by a measurement of at least a second phasor parameter of the utility power as received by at least a second data center. A phase difference between the utility power as received by the first data center and the utility power as received by the second data center can be determined. Whether the phase difference exceeds a threshold value can be determined. Responsive to determining that the phase difference exceeds the threshold value, transfer of at least one workload from the first data center to at least the second data center can be initiated.

A device and method for processing a signal, the method including, by a modulator (1250), receiving an analog signal, modulating the analog signal, and outputting a data frame (1258); receiving, by a counter (1368), the data frame from the modulator and outputting at least two data word sets (1370) each in accordance with a respective one of at least two counter clocks (1372); filtering, by each of at least two digital filter sets (1374), a respective data word set of the at least two data word sets received from the counter, and each outputting, to a switch (1378), a respective filtered data word set (1376). The switch may be configured to select, as an output, one of the filtered data word sets. The switch may be configured to change to a different selected filtered data word set upon detection of a change in line frequency and/or phase.

An A/D conversion device acquires an inter-terminal signal of one or more battery cells when detecting a voltage across the battery cells. The A/D conversion device acquires a failure diagnosis signal during a failure diagnosis. A control unit causes the A/D conversion device to perform A/D conversion processing in a ΔΣ mode or a hybrid mode, in which acquiring remaining bits of higher bits after subjecting the higher bits to a ΔΣ type A/D conversion processing, when detecting the inter-terminal signal of the battery cells. The control unit causes the A/D conversion device to perform the A/D conversion processing in a cyclic mode or a hybrid mode, when detecting the failure diagnosis signal during the failure diagnosis.

A method for reducing an error rate is provided. The method includes obtaining a first analog signal representing a first kinematic property of a first position with a sensor, obtaining a second analog signal representing a second kinematic property of the first position, digitizing the first analog signal into a first digital signal, and digitizing the second analog signal into a second digital signal. The method also includes combining the first digital signal and the second digital signal into a combined signal such that an error rate of the combined signal is less than an error rate of one of the first digital signal and the second digital signal.

The present disclosure relates to an apparatuses and methods for memory management and more particularly to voltage or current detector for a non-volatile memory component that is coupled to a host device or to a System-on-Chip. The memory component includes a memory controller and comprises a voltage or current detector including: a comparator receiving on a voltage input a voltage value Vx; a digital to analog converter coupled to a reference voltage potential and having an output connected to other input of said comparator; a Finite State Machine receiving the output of said comparator and producing digital outputs for the inputs of said memory controller; a current to voltage converter receiving as input a current value Ix to be detected and having an output connected to said Finite State Machine.