Methods and systems for measuring a duty cycle of a signal include applying a first branch of an input signal directly to a latch. A delay of a second branch of the input signal is incrementally increased, with the second branch being applied to the latch, until the latch changes its output. A delay, corresponding to the latch's changed output, is divided by a period of the input signal to determine a duty cycle of the input signal.

Methods and systems for measuring a duty cycle of a signal include applying a first branch of an input signal directly to a latch. A delay of a second branch of the input signal is incrementally increased, with the second branch being applied to the latch, until the latch changes its output. A delay, corresponding to the latch's changed output, is divided by a period of the input signal to determine a duty cycle of the input signal.

A duty cycle-based bit interface system includes a first stage voltage converter and second stage voltage converter in signal communication with the first stage voltage converter. The first stage voltage converter converts a digital voltage signal into an analog voltage signal. The second stage voltage converters convert the digital voltage signal into a scaled version of the same. A sampling unit is in signal communication with at least one of the second stage voltage converters, and is configured to sample a portion of the first stage analog output voltage signal during a sampling time period. The sampled portion has a duty cycle based-analog voltage signal during the sampling time period. A bit selector unit is in signal communication with the sampling unit, and outputs a bit enable signal that initiates a specific diagnostic test among a plurality of diagnostic tests based on the duty cycle of the sampled portion.

A method of assessing a pulse-width-modulated signal in which the pulse-width-modulated signal to be assessed is applied to a first input of a microcontroller and a signal, that depends on the pulse-width-modulated signal being assessed, is applied to a second input of the microcontroller for assessment. The pulse-width-modulated signal being assessed is applied to a voltage divider to produce the signal that depends on the same. For the pulse-width-modulated signal to be assessed and for the signal that depends on the same, in each case, the microcontroller determines a time interval between signal edges of the respective signal, and the signal is assessed on the basis of a difference between the time interval between the signal edges in the pulse-width-modulated signal to be assessed and the time interval between the signal edges in the signal that depends on the same.

Methods and systems for measuring a duty cycle of a signal include applying a first branch of an input signal directly to a latch. A delay of a second branch of the input signal is incrementally increased, with the second branch being applied to the latch, until the latch changes its output. A delay, corresponding to the latch's changed output, is divided by a period of the input signal to determine a duty cycle of the input signal.

A duty cycle-based bit interface system includes a first stage voltage converter and second stage voltage converter in signal communication with the first stage voltage converter. The first stage voltage converter converts a digital voltage signal into an analog voltage signal. The second stage voltage converters convert the digital voltage signal into a scaled version of the same. A sampling unit is in signal communication with at least one of the second stage voltage converters, and is configured to sample a portion of the first stage analog output voltage signal during a sampling time period. The sampled portion has a duty cycle based-analog voltage signal during the sampling time period. A bit selector unit is in signal communication with the sampling unit, and outputs a bit enable signal that initiates a specific diagnostic test among a plurality of diagnostic tests based on the duty cycle of the sampled portion.

An event-driven transmission method comprises converting at least one event to at least one corresponding pulse pair and transmitting the at least one pulse pair. In this context, a delay between each pulse pair represents a corresponding identifier with respect to the respective event or with respect to at least one corresponding object causing or experiencing the respective event.

A fully-digital probabilistic measurement methodology in which a periodic signal generated on an IC device is sampled multiple times during a test period, with the asserted/de-asserted state of the periodic signal determined during each sampling event. A statistically significant number of sampling events are executed according to a reference signal frequency that is uncorrelated to the IC's system clock, whereby each successive sampling event involves detecting an essentially random associated phase of the periodic signal such that the probability of detecting an asserted state during any given sampling event is proportional to the duty cycle of the periodic signal. A first count value records the number of sampling events in which the periodic signal is asserted, and a second count value records the total number of sampling events performed, whereby a ratio of these two count values provides a statistical measurement of the periodic signal's duty cycle.

A high-frequency QRS waveform curve analysis method comprises: acquiring a high-frequency QRS waveform curve; selecting the high-frequency QRS waveform curve in a preset time period as a reference waveform curve; selecting a point with the minimum root-mean-square voltage on the reference waveform curve as a first reference point; selecting a second reference point meeting a first selection condition and a third reference point meeting a second selection condition, wherein the time of the first reference point is later than that of the second reference point and earlier than the third reference point; based on the first reference point and the second reference point, determining an amplitude falling relative value; based on the first reference point and the third reference point, determining an amplitude rising relative value. If the amplitude falling rising relative values meet a preset condition, determining reference information according to the high-frequency QRS waveform curve.

A compensation circuit includes a resistor-capacitor circuit and a control circuit. The resistor-capacitor circuit is used to generate a first voltage when a reference signal is in a first state, and generate a second voltage and a third voltage when the reference signal is in a second state. The resistor-capacitor circuit includes a first resistor-capacitor sub-circuit and a second resistor-capacitor sub-circuit. The first resistor-capacitor sub-circuit and the second resistor-capacitor sub-circuit are coupled to the control circuit, and operate simultaneously to compute an ON time of a front end module. The control circuit is coupled to the resistor-capacitor circuit, and is used to acquire the ON time according to the first voltage, the second voltage, and the third voltage, and includes an adjustment circuit used to generate a bias signal according to the ON time, and output the bias signal to the front end module.