A noise detection circuit includes a first transistor configured to receive a delayed version of a clock signal; a second transistor configured to receive a delayed version of a reference clock signal; and a latch circuit, coupled to the first transistor at a first node and coupled to the second transistor at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on whether a timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.

A noise detection circuit includes a first transistor configured to receive a delayed version of a clock signal; a second transistor configured to receive a delayed version of a reference clock signal; and a latch circuit, coupled to the first transistor at a first node and coupled to the second transistor at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on whether a timing difference between transition edges of the clock signal and the reference clock signal exceeds a pre-defined timing offset threshold.

A power supply glitch detector includes a sense node AC coupled to a power supply node on which voltage glitches having a magnitude of V.sub.glitch are to be detected. A sensing inverter has an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage V.sub.trip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state. An adjustable voltage biasing circuit is coupled to the sensing node to maintain the input of the sensing inverter at a bias voltage V.sub.bias, wherein V.sub.bias is chosen such that either both conditions (V.sub.bias<V.sub.trip) and (V.sub.bias+V.sub.glitch>V.sub.trip) or both conditions (V.sub.bias>V.sub.trip) and (V.sub.biasV.sub.glitch<V.sub.trip) are always true.

A circuit for measuring a transition time of a digital signal may be provided. The circuit comprises a window detector comprising a comparator circuitry arranged for generating a first signal based on comparing said digital signal with a first reference voltage and for generating a second signal based on comparing said digital signal with a second reference voltage. Additionally, the circuit comprises a time-difference-to-digital converter operable for converting a delay between an edge of said first signal and an edge of said second signal into a digital value, said digital value characterizing said transition time of said digital signal.

A circuit for measuring a transition time of a digital signal may be provided. The circuit comprises a window detector comprising a comparator circuitry arranged for generating a first signal based on comparing said digital signal with a first reference voltage and for generating a second signal based on comparing said digital signal with a second reference voltage. Additionally, the circuit comprises a time-difference-to-digital converter operable for converting a delay between an edge of said first signal and an edge of said second signal into a digital value, said digital value characterizing said transition time of said digital signal.

A power supply glitch detector includes a sense node AC coupled to a power supply node on which voltage glitches having a magnitude of V.sub.glitch are to be detected. A sensing inverter has an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage V.sub.trip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state. An adjustable voltage biasing circuit is coupled to the sensing node to maintain the input of the sensing inverter at a bias voltage V.sub.bias, wherein V.sub.bias is chosen such that either both conditions (V.sub.bias<V.sub.trip) and (V.sub.bias+V.sub.glitch>V.sub.trip) or both conditions (V.sub.bias>V.sub.trip) and (V.sub.biasV.sub.glitch<V.sub.trip) are always true.

A method of assessing a pulse-width-modulated signal in which the pulse-width-modulated signal to be assessed is applied to a first input of a microcontroller and a signal, that depends on the pulse-width-modulated signal being assessed, is applied to a second input of the microcontroller for assessment. The pulse-width-modulated signal being assessed is applied to a voltage divider to produce the signal that depends on the same. For the pulse-width-modulated signal to be assessed and for the signal that depends on the same, in each case, the microcontroller determines a time interval between signal edges of the respective signal, and the signal is assessed on the basis of a difference between the time interval between the signal edges in the pulse-width-modulated signal to be assessed and the time interval between the signal edges in the signal that depends on the same.

A monitor for a node of a time division multiple access (TDMA) data bus comprises a logic device configured to calculate a metric of bandwidth use of the TDMA data bus based on monitored signals transmitted by the node, compare of the metric of bandwidth calculated with an expected metric of bandwidth use for the node, determine that a babbling node failure has occurred in response to the metric of bandwidth calculated exceeding the expected metric of bandwidth use for the node, and issue a control signal to reset the node in response to a detected babbling node failure being determined.