A power supply includes: a power factor correction circuit that includes a capacitor and converts an input voltage, produced by rectifying an AC input voltage, to a DC, output voltage; a current detector that detects an inflow current for the power factor correction circuit and outputs a current detection signal; an output voltage detector that detects the output voltage and outputs an output voltage detection signal; a voltage difference detector that detects a voltage difference between maximum and minimum values of a pulsation component of the output voltage detected from the output voltage detection signal; a working life determiner that compares the voltage difference and a threshold and gives notification of end of life of the capacitor when the voltage difference reaches the threshold; and a threshold updater that updates the threshold in keeping with the detected inflow current detected based on the current detection signal.

The present disclosure relates to a semiconductor integrated circuit and a signal processing method that can improve measurement accuracy. Pulses subjected to pulse generation and disconnection control by a control circuit are supplied to a pulse distribution circuit and a CP circuit. The pulse distribution circuit divides one pulse into two or more pulses that do not overlap each other, and supplies the pulses to a CBCM circuit. The CBCM circuit is configured by connecting a capacitance element to be measured to the output of a measurement core circuit called a pseudo inverter. The CP circuit inputs, to the gate electrode, pulses that cause a channel of a non-measurement MISFET to change from the accumulation state to the inverted state, and monitors, from the substrate side, a CP current flowing through a trap acting as a recombination center of the gate insulating film and the semiconductor substrate interface. The present disclosure can be applied to, for example, a semiconductor integrated circuit for evaluating the characteristics of the gate insulating film of the MISFET.

The present invention is directed to a multilayer ceramic capacitor that includes a plurality of active electrodes and at least one shield electrode that are each arranged within a monolithic body and parallel with a longitudinal direction. The capacitor may exhibit a first insertion loss value at a test frequency, which may be greater than about 2 GHz, in a first orientation relative to the mounting surface. The capacitor may exhibit a second insertion loss value at about the test frequency in a second orientation relative to the mounting surface and the capacitor is rotated 90 degrees or more about the longitudinal direction with respect to the first orientation. The longitudinal direction of the capacitor may be parallel with the mounting surface in each of the first and second orientations. The second insertion loss value may differ from the first insertion loss value by at least about 0.3 dB.

A method for determining an electrical capacitance in an intermediate circuit of an electric drive system. The electric drive system includes at least one first electrical energy source, which feeds the intermediate circuit, a drive unit, which has an inverter and an electrical load, the inverter being electrically connected on the input side with the intermediate circuit and on the output side with the electrical load, and a DC voltage converter, which is electrically connected with the intermediate circuit and measures a voltage in the intermediate circuit by high frequency sampling. The electrical capacitance in the intermediate circuit is determined from the voltage in the intermediate circuit measured by the DC voltage converter. Also described is a motor vehicle, which includes an electric drive system for implementing the method.

A method and an apparatus are disclosed for providing an indication of a capacitor fault in a given string of a capacitor bank comprising at least one string mounted in parallel, each string comprising a plurality of capacitor elements connected in series. The method comprises obtaining a capacitor bank voltage, the obtaining comprising measuring a voltage across the capacitor bank; obtaining a current of the given string, the obtaining of the current of the given string comprising measuring a current flowing in the given string of the capacitor bank; determining a measured impedance at a grid frequency using the obtained capacitor bank voltage and the obtained current of the given string; providing an indication of a capacitor fault if a difference between the measured impedance and a previously measured impedance exceeds a first given threshold for a first given duration.

Described is a CBCM technique that works only with PMOS transistors or only with NMOS transistors. Specifically, a method of monitoring performance of an integrated circuit device using a CBCM technique is disclosed, the method comprising: providing a metrology structure having a pseudo-inverter comprising a pull-up pull-down transistor switch, wherein the transistor switch comprises a pull-up transistor and a pull-down transistor of the same type; charging and discharging a device under test (DUT) coupled to the pseudo-inverter using a non-overlapping clock; measuring capacitance of the DUT with a gate voltage of the pull-up transistor at a preset value; and, using the value of the measured capacitance to estimate a dimension of a structure in the integrated circuit device. The non-overlapping clock is generated by: turning the pull-down transistor off when the pull-up transistor is on; and, turning the pull-down transistor on when the pull-up transistor is off.

A driver circuit driving a plurality of capacitive loads includes: a plurality of output terminals to which the plurality of capacitive loads are to be connected; a plurality of drivers corresponding to the plurality of output terminals, each of the plurality of drivers being configured to generate a drive signal to be applied to each of the plurality of capacitive loads respectively corresponding to the plurality of drivers; and a capacitance detection circuit configured to detect a capacitance associated with each of the plurality of output terminals.

A method of iteratively screening a sample of electrolytic capacitors having a predetermined rated voltage is provided. The method can include measuring a first leakage current of a first set of capacitors, calculating a first mean leakage current therefrom, and removing capacitors from the first set having a first leakage current equal to or above a first predetermined value, thereby forming a second set of capacitors. The second set can be subjected to a burn in heat treatment where a test voltage can be applied, then a second leakage current of the second set of capacitors can be measured and a second mean leakage current can be calculated. Capacitors having a second leakage current equal to or above a second predetermined value can be removed from the second set, forming a third set of capacitors. Because of such iterative screening, the capacitors in the third set have low failure rates.

A current measurement apparatus comprises: a capacitor connected in parallel to a signal terminal of a device under test (DUT); a test pattern generation apparatus generating a test pattern to operate the DUT; and a measurement module connected to one end of the capacitor. The measurement module comprises: an input/output (I/O) buffer increasing or reducing an amount of charges of the capacitor and outputting a signal corresponding to an output logic value according to a voltage of the one end of the capacitor; a time measurer measuring an arrival time which it takes for the voltage of the one end of the capacitor to reach a second voltage from a first voltage; and a controller controlling the i/o buffer and the time measurer to measure the arrival time and controlling such that a value of a current related to an inspection of a DUT is measured using the arrival time.

One preferable aspect of the present invention is a state detecting system which detects a state of a machine device based on a detection signal from a detecting element provided to the machine device, and is the state detecting system which includes a non-normal time rate detecting unit which detects a rate or a value as a non-normal time rate, the rate being a rate of an integration value of a time during which an amplitude of the detection signal exceeds a predetermined normal amplitude within a predetermined time, and the value being physically equivalent to the rate.