A test system and test techniques for accurate high-current parametric testing of semiconductor devices. In operation, the test system supplies a current to the semiconductor device and measures a voltage on the device. The testing system may use the measured voltage to compute an ON resistance for the high-current semiconductor device. In one technique, multiple force needles contact a pad in positions that provide equi-resistant paths to one or more sense needles contacting the same pad. In another technique, current flow through the force needles is regulated such that voltage at the pad of the device under test is representative of the ON resistance of the device and independent of contact resistance of the force needle. Another technique entails generating an alarm indication when the contact resistance of a force needle exceeds a threshold.

A system includes a controller that is configured to generate a plurality of switch control signals; a plurality of electrical circuit elements, the plurality of electrical circuit elements being characterized by a plurality of impedances, respectively; a plurality of voltage sources; and a plurality of switches that are programmable to couple the plurality of electrical circuit elements to the plurality of voltage sources responsive to the plurality of switch control signals.

A semiconductor test circuit, apparatus, and method having a first relay disposed between a power supply and a switching element, a second relay disposed between a connection point of the switching element and a reverse conducting-insulated gate bipolar transistor (RC-IGBT) chip and a snubber circuit, a third relay disposed between the switching element and the RC-IGBT chip and a coil, and a fourth relay disposed between a diode and the switching element. A turn on/off test of an IGBT portion is performed by turning on the second and fourth relays. An avalanche test of the IGBT portion is performed by turning on the second relay. A short-circuit test of the IGBT portion is performed by turning on the first relay. A recovery test of an FWD portion is performed by turning on the first and third relays. At this time probes are brought into contact with electrodes once.

A semiconductor module, including a cooler having first and second flow passages respectively formed on first and second sides of the semiconductor module that are opposite to each other, and a third flow passage connecting the first and second flow passages. The semiconductor module further includes a laminated substrate disposed on the cooler and having first to third circuit boards, a first sensing chip having a sensing function for detecting a temperature and a first non-sensing chip not having the sensing function, disposed on the first circuit board side by side along the third flow passage, and a second sensing chip having the sensing function and a second non-sensing chip not having the sensing function, disposed on the third circuit board side by side along the third flow passage. The first and second sensing chips are respectively disposed on the second side and the first side of the semiconductor module.

A system is provided. The system includes a semi-conductor device and a gate drive board. The gate drive board provides a voltage to the semi-conductor device. The system also includes a controller and a monitoring circuit. The controller drives the voltage provided by the gate drive board. The monitoring circuit is coupled to the gate drive board to monitor operations of the controller and the semi-conductor device.

Disclosed are an IGBT-module condition monitoring equipment and method. The IGBT-module condition monitoring equipment includes an IGBT module, a gate turning-on voltage overshoot monitoring module, a driving circuit, a bond wire state judging module, and a signal acquisition module. The breakage condition of bond wires is obtained by comparing a monitored actual gate turning-on voltage overshoot with a preset reference gate turning-on voltage overshoot threshold. The present invention solves the problem encountered in monitoring the aging of IGBT bond wires in power electronic converters. By characterizing the bond wire detachment with the gate turning-on voltage overshoot, the slight aging of the detached bond wires can be monitored without disturbing the operation, which is high in resolution and free of invasiveness and enables real-time online monitoring at high sampling rate and low cost, showing great significance in the monitoring of the IGBT and the reliability evaluation of power electronic converters.

An apparatus includes an inverter configured to be connected to a load, a driver having an output coupled to control terminals of transistors of the inverter and a control input configured to receive control vectors and responsively apply control signals to control terminals of the inverter, a desaturation detector configured to detect desaturation of the transistors, and a controller coupled to the control input of the driver and configured to apply at least one test vector that causes the driver to turn on selected ones of the transistors for a duration sufficient for the desaturation detector to detect desaturation of at least one of the selected transistors and to enable or inhibit further operation of the inverter responsive to the desaturation detector. The load may be a motor and the controller may be configured to apply the at least one test vector responsive to a command to start the motor.

The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices including a metal-oxide-semiconductor (MOS) transistor and are configured for accelerating and monitoring degradation of the gate dielectric of the MOS transistor. In one aspect, a semiconductor device configured with gate dielectric monitoring capability comprises a metal-oxide-semiconductor (MOS) transistor including a source, a drain, a gate, and a backgate region formed in a semiconductor substrate. The semiconductor device additionally comprises a bipolar junction transistor (BJT) including a collector, a base, and an emitter formed in the semiconductor substrate, wherein the backgate region of the MOS transistor serves as the base of the BJT and is independently accessible for activating the BJT. The MOS transistor and the BJT are configured to be concurrently activated by biasing the backgate region independently from the source of the MOS transistor, such that the base of the BJT injects carriers of a first charge type into the backgate region of the MOS transistor, where the first charge type is opposite charge type to channel current carriers.

The present invention concerns a method and a device (10) for monitoring a multi-die power module (15) comprising dies that are in a half-bridge switch configuration. The invention: sets the dies in a non conductive state, selects one die which is blocking a voltage, injects a current in a gate of the selected die in order to charge an input parasitic capacitance of the selected die, monitors a voltage that is representative of a voltage on the gate of the selected die, memorizes the value of the monitored voltage when the value of the monitored voltage is stabilized.

A multi-die health monitoring device: sets, at a given current provided to the load by the group of dies, one of the dies in a non-conducting state (NCS), obtains, when the die is in the NCS, a signal that is representative of the temperature of the die and determines the temperature of the die, obtains, when the die is in the NCS, a signal that is representative of an on-state voltage (OSV) of the die and determines the OSV of the die, retrieves in a table stored in a memory of the multi-die health monitoring device, an OSV that corresponds to the given current and the determined temperature of the die, notifies that the multi-die power module has to be replaced, if the difference between the determined OSV of the die and the retrieved OSV is equal or upper than a predetermined value.