The present invention provides a system and method for measuring intermittent operating life (IOL) of a GaN-based device under test (DUT) is provided. The system is operable in a stressing mode, a cooling mode and a measure mode. A power regulation approach is adopted to ensure that DUT of the same thermal resistance have same temperature increase during the IOL test. The present invention eliminates the influence caused by parasitic parameters of testing circuits and the inconsistency of threshold voltage and drain-source resistance of the device itself. Through power regulation, it is the junction temperature of the device, not the housing temperature of the device, being directly controlled. Therefore, higher measurement accuracy can be achieved.

A semiconductor structure and a method of manufacturing a semiconductor structure are provided. The method includes forming a conductive layer on a precursor memory structure, in which the precursor memory structure includes a plurality of transistors and a plurality of contact plugs disposed on and connected to the transistors. The conductive layer in a TEG region is then patterned to form a first patterned conductive layer on the precursor memory structure. The first patterned conductive layer is then patterned to form a plurality of first landing pads extending along a first direction, in which the first landing pads are separated from each other in a second direction that is different from the first direction and are electrically connected to each other through the contact plugs and the transistors.

A power semiconductor module including at least first and second power semiconductor elements, includes a first terminal, a first gate terminal, a second terminal, a second gate terminal, a third terminal and a common terminal. The first terminal connected to a first electrode of the first power semiconductor element. The first gate terminal connected to a gate of the first power semiconductor element. The second terminal connected to a first electrode of the second power semiconductor element. The second gate terminal connected to a gate of the second power semiconductor element. The third terminal connected to a second electrode of the first power semiconductor element and a second electrode of the second power semiconductor element. The common terminal that is connected to the first gate terminal through a first resistor and is connected to the second gate terminal through a second resistor.

The subject application provides an apparatus and method for measuring dynamic on-resistance of a device under test (DUT) comprising a control terminal electrically connected to an output of a first controlling module being configured to generate a first control signal to switch on and off the DUT. The apparatus comprises a switching device and a second controlling module configured to: receive the first control signal from the first controlling module and generate a second control signal to switch on and off the switching device such that the switching device is turned on later than the DUT for a first time interval and turned off earlier than the DUT for a second time interval.

A device includes FETs with control terminals. A gate driver circuit causes the FETs to turn on and to enter a high-impedance state in response to an OCP signal. A current sense circuit senses an FET current through the FETs and sends the OCP signal to the gate driver circuit when the FET current exceeds an OCP current for longer than an OCP deglitch period. A test sequencer, in response to receiving an external test mode signal, sets the OCP current to a preset OCP test current, sets the OCP deglitch period to a preset OCP deglitch test period, and causes the gate driver circuit to turn on the plurality of FETs.

An integrated circuit with a switched signal path and circuitry configured to determine an anticipated specification current through the signal path.

The present disclosure provides a process corner detection circuit and a process corner detection method. The process corner detection circuit includes: M ring oscillators disposed inside a chip, M≥1, where types of N-type transistors in the M ring oscillators are not exactly the same, and types of P-type transistors in the M ring oscillators are not exactly the same; transistor types of the M ring oscillators include all transistor types used in the chip; the ring oscillators include symmetric ring oscillators and asymmetric ring oscillators; types of N-type transistors and P-type transistors in the symmetric ring oscillators are the same; and types of N-type transistors and P-type transistors in the asymmetric ring oscillators are different.

Embodiments of the invention provide for integrated circuits for testing one or more transistors for process variation effects. According to an embodiment, the integrated circuit can include: a plurality of ring oscillator macro circuits, wherein each ring oscillator macro circuit includes two ring oscillators, a first multiplexer, and a first divide-by-two circuit; a multiplexer stage; a divide-by-two circuit stage; a second multiplexer; a second divide-by-two circuit; and frequency measurement circuit. According to another embodiment, the integrated circuit can include: a first shift register including a plurality of devices-under-test; a second shift register including a plurality of static latches; a first multiplexer configured to receive outputs from each of the plurality of DUTs; a second multiplexer configured to receive outputs from each of the plurality of static latches; and a comparator configured to compare an output from the first multiplexer with an output from the second multiplexer.

A fault detection circuit includes a short circuit comparison circuit which has a first input connected to the source of the second NFET, a second input, and an output. The circuit includes an over-current comparison circuit which has a first input connected to the source of the second NFET, a second input, and an output. The circuit includes a voltage divider circuit which has a first terminal connected to first input of the short circuit comparison circuit, a second terminal connected to the first input of the over-current comparison circuit, and a third terminal connected to a ground terminal. The circuit includes a delay circuit which has an input connected to the output of the over-current comparison circuit and has an output.

A device includes FETs with control terminals. A gate driver circuit causes the FETs to turn on and to enter a high-impedance state in response to an OCP signal. A current sense circuit senses an FET current through the FETs and sends the OCP signal to the gate driver circuit when the FET current exceeds an OCP current for longer than an OCP deglitch period. A test sequencer, in response to receiving an external test mode signal, sets the OCP current to a preset OCP test current, sets the OCP deglitch period to a preset OCP deglitch test period, and causes the gate driver circuit to turn on the plurality of FETs.