A test verification circuit is described herein for verifying proper operation of a tested circuit, such as a voltage hazard warning circuit, using an N-channel MOSFET configured for switching ON and OFF the test verification circuit during a power outage, and a voltage source that provides an input voltage to the N-channel MOSFET from a conserved power supply. The N-channel MOSFET provides temporary power from a conserved power supply to the test verification circuit upon activation by a user during a power outage, and the test verification circuit determines whether the tested circuit has been de-energized, remains energized, or there remains inadequate power to complete the test.

A monitoring device is provided for monitoring a semiconductor-based switching element having a control input, a power input, and a power output. The monitoring device includes a charge carrier source for charging the control input of the switching element with electric charge carriers, and a measuring device for detecting a charge carrier drain from the control input of the switching element. The measuring device emits a warning signal if the charge carrier drain lies above a specified threshold value. A corresponding method for monitoring a semiconductor-based switching element is also provided.

A switching network includes a switch, a driver for the switch, and a floating-regulator that powers the driver. The floating-regulator includes a shunt that is used only when testing the network. The shunt diverts biasing current so that it does not interfere with a measurement of an electrical property of a switch.

A method of determining whether a silicon-carbide semiconductor device, which has a metal oxide semiconductor (MOS) gate structure and a built-in diode, is a conforming product. The method includes measuring an ON voltage of the silicon carbide semiconductor device, passing a forward current through the built-in diode of the silicon carbide semiconductor device, measuring another ON voltage of the silicon carbide semiconductor device, which is the ON voltage of the silicon carbide semiconductor device after passing the forward current, calculating a rate of change between the ON voltage and the another ON voltage, and determining that the silicon carbide semiconductor device is a conforming product unless the calculated rate of change is less than 3%.

A semiconductor device includes a first test structure including a first portion of a conductive structure and a second portion of the conductive structure located within a first lateral wiring layer of a layer stack of the semiconductor device. The first portion of the conductive structure of the first test structure is electrically connected to the second portion of the conductive structure of the first test structure through a third portion located within a second lateral wiring layer of the layer stack arranged above the first lateral wiring layer. Further, the first portion of the conductive structure of the first test structure is electrically connected to a gate of a test transistor structure, a doping region of the test transistor structure or an electrode of a test capacitor. Additionally, the first portion of the conductive structure of the first test structure is electrically connected to a first test pad of the first test structure.

A test structure for a semiconductor device, comprising a device under test including a transistor, the transistor having a gate electrode, a source electrode, a drain electrode and a bulk electrode, a first fuse and a second fuse provided in series, wherein one terminal of the first fuse is connected to the gate electrode, one terminal of the second fuse is connected to the bulk electrode, the other terminal of the first fuse and the other terminal of the second fuse being connected to each other, a first input/output pad connected to the first terminal of the first fuse and to the gate electrode of the transistor, a second input/output pad connected to the first terminal of the second fuse and to the bulk electrode of the transistor, a third input/output pad connected to the second terminal of the first fuse and the second terminal of the second fuse.

Systems, devices, methods, and techniques are disclosed for open load detection in the connections coming from output stages of electrical systems.

An approach for determining leakage current and threshold voltage for ensemble semiconductor devices, implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having program instructions, are operable to: receive a number m of individual devices within an ensemble device; identify a sub-threshold slope; determine an uplift factor; separate random variation in logarithm of a leakage current into a correlated random component and an uncorrelated random component; determine a first standard deviation of correlated random component for the ensemble device; determine a second standard deviation of the uncorrelated random component for the ensemble device; generate a statistical model for electrical features of the ensemble device, based on the number m of individual devices, the sub-threshold slope, the uplift factor, the first and second standard deviation, and statistical random variables; and determine the electrical features of the ensemble device based on the statistical model.

A method for measuring a current-voltage characteristic (Id-Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id-Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.

The semiconductor inspection apparatus according to an embodiment includes a first detecting unit capable of being electrically connected to a source electrode of a field effect transistor to be evaluated, the first detecting unit used for detecting voltage, a first diode including a first anode electrode and a first cathode electrode, the first cathode electrode capable of being electrically connected to a drain electrode of the field effect transistor, a second detecting unit electrically connected to the first anode electrode, the second detecting unit used for detecting voltage, a first resistance element of which a first end is electrically connected to the first anode electrode, and a first electric power source electrically connected to a second end of the first resistance element.