A device and method for limiting damage to a semiconductor device under test when the semiconductor device fails during a high current, or high power test is provided. The occurrence of a failure of the device under test is detected, and power applied to the semiconductor device is diverted through a parallel path element upon detection of failure of the semiconductor device.

Disclosed examples include systems to determine an on-state impedance of a high voltage transistor, and measurement circuits to measure the drain voltage of a drain terminal of the high voltage transistor during switching, including an attenuator circuit to generate an attenuator output signal representing a voltage across the high voltage transistor when the high voltage transistor is turned on, and a differential amplifier to provide an amplified sense voltage signal according to the attenuator output signal. The attenuator circuit includes a clamp transistor coupled with the drain terminal of the high voltage transistor to provide a sense signal to a first internal node, a resistive voltage divider circuit to provide the attenuator output signal based on the sense signal, and a first clamp circuit to limit the sense signal voltage when the high voltage transistor is turned off.

An online monitoring system for measuring the on-state voltage drop of power semiconductor devices comprises a voltage withstanding circuit and a voltage clamping circuit, one terminal of the voltage withstanding circuit is connected to one terminal of the voltage clamping circuit, and the other terminals of the voltage withstanding circuit and the voltage clamping circuit are randomly connected to two terminals of the power semiconductor device under test (DUT) respectively. The two terminals of the voltage clamping circuit are output terminals of the online monitoring system. A clamping voltage of the voltage clamping circuit is higher than the on-state voltage drop of the DUT. When the DUT is off, the output voltage of the system is fixed to the clamping voltage, and when it is on, the output voltage is not clamped. The system has simplified structure and enables convenient, accurate and low-cost measurement of on-state voltage drop.

A method of monitoring a condition of a SiC MOSFET can include (a) applying a first test gate-source voltage across a gate-source of a SiC MOSFET in-situ, the first test gate-source voltage configured to operate the SiC MOSFET in saturation mode to generate a first drain current in the SiC MOSFET, (b) applying a second test gate-source voltage across the gate-source of the SiC MOSFET in-situ, the second test gate-source voltage configured to operate the SiC MOSFET in fully-on mode to generate a second drain current in the SiC MOSFET, (c) determining a drain-source saturation resistance using the first drain current to provide an indication of a degradation of a gate oxide of the SiC MOSFET; and (d) determining a drain-source on resistance using the second drain current to provide an indication of a degradation of contact resistance of the SiC MOSFET.

The present application discloses a method and apparatus for calculating the kink current of SOI device, which is used to solve the problem that the kink current calculation in the prior art is not accurate and is not suitable for circuit simulation. The method includes: obtaining the impact ionization factor, the parasitic transistor effect factor, and the drain saturation current of the SOI device respectively; and calculating the kink current of the SOI device according to the impact ionization factor, the parasitic transistor effect factor, and the drain saturation current.

A circuit and diagnosis method capable of individually diagnosing abnormality of a plurality of internal FETs constituting a MOSFET provided between a secondary battery pack and an electric vehicle. Voltage at both ends of each of the internal FETs is measured while individually turning ON/OFF the internal FETs, and is compared with a diagnosis table in order to determine abnormality thereof.

A method is for testing the functionality of a switching member including at least one switching element. A switching state is influenced via a control input of the switching element and via a control signal generated and output to the control input. An activation signal is output to the control unit and changes the control signal. The activation signal induces a test signal as the change to the control signal and induces a disconnection pulse as the test signal. The SiC or GaN power semiconductor is switched off via the disconnection pulse and conducts current in the reverse direction. In response to the disconnection pulse, the voltage drop is recorded. A comparison is carried out between an indicator and a reference encoding an expected response to the disconnection pulse. Depending on the result of the comparison, a status signal is generated which encodes the functionality of the switching member.

An effect of PID is measured with higher accuracy by using an oscillation circuit. There is provided a semiconductor device including at least one measurement transistor a gate of which is electrically connected to an antenna unit that functions as an antenna in a plasma process, a selection transistor a source of which is electrically connected to the gate of the measurement transistor in parallel to the antenna unit; and an oscillation circuit electrically connected to a source of the measurement transistor and having an oscillation frequency that changes according to a threshold voltage of the measurement transistor.

Test structures for a body-contacted field effect transistor (BCFET) include: a single-pad structure with body contact and probe pad regions connected to a channel region at first and second connection points with a known separation distance between the connection points; and a multi-pad structure with a body contact region connected to a channel region at a first connection point and multiple probe pad regions connected to the channel region at second connection points that are separated from the first connection point by different separation distances. A method includes: determining separation distance-dependent internal body potentials at the second connection points in response to different bias conditions by using either multiple single-pad structures, each having a different separation distance between the connection points, or by using a multi-pad structure; and based on the separation distance-dependent internal body potentials, generating a model representing the BCFET with body-contacted and floating body devices.

Laser-assisted integrated circuit (IC) device testing apparatus capable of inducing hot carrier injection (HCI) within selected transistors of an IC device. A laser source of sufficiently high output power (e.g., 1W) and short pulse duration (e.g., 100 fs) can generate enough hot carriers through a multi-photon (e.g., TPA) carrier injection mechanism to significantly accelerate HCI aging even at low transistor voltage bias (e.g., <1.5V). Rapid laser-assisted HCI transistor aging can selectively degrade transistors of individual functional IC blocks within an IC device.