Patent classifications
G01R31/2637
Fabrication of a sacrificial interposer test structure
A sacrificial interposer test structure including a release layer, a dummy layer on the release layer, one or more conductive pads embedded in the dummy layer, wherein each of the one or more conductive pads has an exposed surface, and a tie layer on the dummy layer and on each exposed surface of the one or more conductive pads.
Method for estimating power system health
A method of monitoring the health of a semiconductor power electronic switch such as an insulated gate bipolar transistor (IGBT) is provided. The method having the steps of: measuring one or more parameters selected from the group consisting of: a rate of change of voltage
across the switch; a rate of change of current
through the switch, a charge present on a gate of the switch (Q.sub.G), a peak overshoot voltage (V.sub.PO) across the switch, and a peak overshoot or reverse recovery current (I.sub.RR) through the switch; and estimating the health of the switch based on the measured parameter(s).
DUMMY ELEMENT AND METHOD OF EXAMINING DEFECT OF RESISTIVE ELEMENT
A dummy element includes: a semiconductor substrate; a lower insulating film deposited on the semiconductor substrate; a first resistive layer deposited on the lower insulating film; an interlayer insulating film covering the first resistive layer; a first pad-forming electrode deposited on the interlayer insulating film so as to be connected to the first resistive layer, and including an extending portion to be in Schottky contact with the semiconductor substrate; a relay wire connected to the first resistive layer and connected to the semiconductor substrate with an ohmic contact; and a counter electrode allocated under the semiconductor substrate, the dummy element simulating a defective state in the lower insulating film and the interlayer insulating film immediately under the first pad-forming electrode included in a corresponding resistive element as a target to be examined.
SEMI-INSULATING COMPOUND SEMICONDUCTOR SUBSTRATE AND SEMI-INSULATING COMPOUND SEMICONDUCTOR SINGLE CRYSTAL
A semi-insulating compound semiconductor substrate includes a semi-insulating compound semiconductor, the semi-insulating compound semiconductor substrate being configured such that, on a major plane having a plane orientation of (100), a standard deviation/average value of specific resistance measured at intervals of 0.1 mm along equivalent four directions in a <110> direction from a center of the major plane, and a standard deviation/average value of specific resistance measured at intervals of 0.1 mm along equivalent four directions in a <100> direction from the center of the major plane are each not more than 0.1.
APPARATUS FOR ESTIMATING LIFETIME OF THE SPD USING DISCHARGE CHARACTERISTICS OF THE MOV
An apparatus for estimating the lifetime of a surge protective device (SPD) using the discharge characteristics of a metal oxide varistor (MOV) includes an MOV having an input terminal and an output terminal; an impulse voltage application unit applying an impulse voltage for MOV test to the input terminal of the MOV; a discharge current measurement unit; a first switching unit connecting a power line to the input terminal of the MOV; a second switching unit connecting a ground line to the output terminal of the MOV in the normal mode and selectively connecting the discharge current measurement unit in the MOV test mode; an MOV test management unit providing information; a discharge current check unit generating an MOV abnormal signal; and an MOV state display unit displaying an MOV abnormal signal.
TESTING DEVICE, TESTING METHOD, AND NON-TRANSITORY STORAGE MEDIUM STORING TESTING PROGRAM
A testing device includes a contactless measurement unit configured to measure a thickness of a test object and a probe needle configured to move by a distance in accordance with the thickness measured by the measurement unit to come into contact with an electrode of the test object.
THERMOPILE SELF-TEST AND/OR SELF-CALIBRATION
We disclose herein a method for testing and/or calibrating a thermopile based device. The method comprising: applying an electrical bias of a first polarity to the thermopile based device and measuring a first value of an electrical parameter; and applying an electrical bias of a second polarity to the thermopile based device and measuring a second value of an electrical parameter.
Semiconductor device
Considering ease of electrical conduction tests and the like, electrodes provided mainly above an active region are desirably continuous on a single plane. A semiconductor device is provided, including: a semiconductor substrate; a first top surface electrode and a second top surface electrode that are provided above a top surface of the semiconductor substrate and contain a metal material; and a first connecting portion that electrically connects to the first top surface electrode and contains a semiconductor material, wherein the second top surface electrode has: a first region and a second region that are arranged being separated from each other with the first connecting portion as a boundary in a top view of the semiconductor substrate, and a second connecting portion that connects the first region and the second region above the first connecting portion.
Apparatus for determining deterioration of photocoupler
An apparatus is provided to determine deterioration of a photocoupler. The apparatus includes a detecting unit and a determining unit. The detecting unit receives an electric pulse signal outputted from the photocoupler. The amplitude of the outputted pulse signal depends on that of an electric AC voltage applied to the photocoupler. The detecting unit detects a duty ratio of the pulse signal. The determining unit determines whether or not the duty ratio is less than a threshold given for the determination. The determining unit also determines that the photocoupler has deteriorated in performance thereof more than a usable level if it is determined that the duty ratio is less than the threshold given for the determination.
Pipe structure and semiconductor module testing equipment including the same
Semiconductor module testing equipment includes a test board, a plurality of pipe structures extending from an upper surface of the test board in a first direction and spaced apart from one another in a second direction that intersects the first direction, wherein the first and second directions are substantially parallel to a plane of the test board, at least one semiconductor module socket disposed between a pair of neighboring pipe structures of the plurality of pipe structures, and a plurality of nozzles disposed on each pipe structure of the plurality of pipe structures, wherein the plurality of nozzles is configured to discharge a fluid laterally.