G01R31/2637

Current application device and manufacturing method of semiconductor element

Provided is a current application device capable of applying a test current of a magnitude necessary for testing of a semiconductor element without any trouble. A current application device 1 is configured to have a contacting section having a plurality of projections 21 for contacting a contact region 24 inside an active region 23 of a semiconductor element 22 and applying the test current thereto, and a pressing section 3 which presses the contacting section 2 against the semiconductor element 22 such that each projection 21 contacts the contact region 24. A plurality of the projections 21 are arranged such that an arrangement density of outside projections 21 is larger than the arrangement density of inside projections 21.

DEVICE AND METHOD FOR CHARACTERIZING THE CURRENT COLLAPSE OF GAN TRANSISTORS

A device for evaluating a dynamic resistance in a conducting state of a GaN-based transistor. The device including a test circuit provided with a circuit, the GaN-based transistor, forming an arm of the circuit, the device being provided with a stage for controlling the switch elements of the circuit to alternately set the switch elements of the circuit in a first configuration and then in a second configuration, the control stage being configured to trigger a connection of a drain-source voltage measuring stage to the GaN-based transistor after the circuit is set in the first configuration, and to trigger a disconnection of the drain-source voltage measuring stage from the GaN-based transistor before the circuit is set in the second configuration.

Bonding quality test method, bonding quality test circuit, and memory device including bonding quality test circuit
12422466 · 2025-09-23 · ·

A bonding quality test circuit includes a switching circuit configured to provide a connection between a sensing node and a bonding node, the bonding node corresponding to a first end of a bonding resistor that is between a line provided to a memory device and a peripheral circuit, a precharging circuit configured to provide a precharge voltage to the line and the sensing node when the precharging circuit is connected to the line and the sensing node by the switching circuit, a latch circuit that includes a first node configured to provide a control output signal to the precharging circuit and a second node configured to have a voltage that is phase inverted with respect to a voltage of the control output signal, and a first transistor configured to provide an output signal according to the sensing node when the first transistor is connected to the second node.